Spelling and space cleanup

Documentation/developer/regression_tests.rst

@@ -8,7 +8,7 @@ suite, and this suite is used by the github actions as continuous integration
 to make sure the code is always going forward.
 
 NOTE: There are scripts written in perl to run the regression tests, but they
-are bing gradually replaced with a newer set of scripts. It is the newer
+are being gradually replaced with a newer set of scripts. It is the newer
 method that is described here.
 
 Test Descriptions

Documentation/targets/pcb.rst

@@ -55,7 +55,7 @@ Verilog parameter override syntax. Parameters have preferred types.
   is written into the description field of the PCB Element.
 
 * value (string, default="")
-  
+
   The "value" is a text tring that describes some value for the black
   box. Like the description, the code generator does not interpret this value,
   other then to write it to the appropriate field in the PCB Element."

Documentation/targets/verilog95.rst

@@ -42,21 +42,21 @@ Structures that cannot be converted to 1995 compatible Verilog
 The following Verilog constructs are not translatable to 1995 compatible Verilog:
 
 * Automatic tasks or functions.
-  
+
 * The power operator (**). Expressions of the form (2**N)**<variable> (where N
   is a constant) can be converter to a shift.
-  
+
 * Some System Verilog constructs (e.g. final blocks, ++/-- operators,
   etc.). 2-state variables are converted to 4-state variables.
 
 Icarus extensions that cannot be translated:
 
 * Integer constants greater than 32 bits.
-  
+
 * Real valued nets.
-  
+
 * Real modulus.
-  
+
 * Most Verilog-A constructs.
 
 

Documentation/usage/command_files.rst

@@ -124,7 +124,7 @@ list of the special records with their meaning.
   have multiple directories, separated by "+" characters.
 
 * +libdir-nocase+dir-path
-  
+
   This is the same as "+libdir+", but when searching "nocase" libraries for
   module files, case will not be taken as significant. This is useful when the
   library is on a case insensitive file system.
@@ -136,7 +136,7 @@ list of the special records with their meaning.
   variety of naming conventions.
 
 * -y dir-path
-  
+
   This is like "+libdir+" but each line takes only one path. Like "+libdir+"
   there can be multiple "-y" records to declare multiple library
   directories. This is similar to the "-y" flag on the iverilog command line.
@@ -151,19 +151,19 @@ list of the special records with their meaning.
   in releases and snapshots made after that date.
 
 * +incdir+*include-dir-path*
-  
+
   Declare a directory or list of directories to search for files included by
   the "include" compiler directive. The directories are searched in
   order. This is similar to the "-I" flag on the iverilog command line.
 
 * +define+*name=value*
-  
+
   Define the preprocessor symbol "name" to have the string value "value". If
   the value (and the "=") are omitted, then it is assumed to be the string
   "1". This is similar to the "-D" on the iverilog command line.
 
 * +timescale+*units/precision*
-  
+
   Define the default timescale. This is the timescale that is used if there is
   no other timescale directive in the Verilog source. The compiler default
   default is "+timescale+1s/1s", which this command file setting can
@@ -171,7 +171,7 @@ list of the special records with their meaning.
   timescale directive in the verilog source.
 
 * +toupper-filename
-  
+
   This token causes file names after this in the command file to be translated
   to uppercase. this helps with situations where a directory has passed
   through a DOS machine (or a FAT file system) and in the process the file
@@ -179,11 +179,11 @@ list of the special records with their meaning.
   emergencies.
 
 * +tolower-filename
-  
+
   The is the lowercase version of "+toupper-filename".
 
 * +parameter+*name=value*
-  
+
   This token causes the compiler to override a parameter value for a top-level
   module. For example, if the module main has the parameter WIDTH, set the
   width like this "+parameter+main.WIDTH=5". Note the use of the complete
@@ -191,7 +191,7 @@ list of the special records with their meaning.
   (top level) modules and a defparam may override the command file value.
 
 * +vhdl-work+*path*
-  
+
   When compiling VHDL, this token allows control over the directory to use for
   holding working package declarations. For example, "+vhdl-work+workdir" will
   cause the directory "workdir" to be used as a directory for holding working

Documentation/usage/command_line_flags.rst

@@ -14,17 +14,17 @@ General
 These flags affect the general behavior of the compiler.
 
 * -c <cmdfile>
-  
+
   This flag selects the command file to use. The command file is an
   alternative to writing a long command line with a lot of file names and
   compiler flags. See the Command File Format page for more information.
 
 * -d <flag>
-  
+
   Enable compiler debug output. These are aids for debugging Icarus Verilog,
   and this flag is not commonly used.
   The flag is one of these debug classes:
-  
+
   * scope
   * eval_tree
   * elaborate
@@ -40,15 +40,15 @@ These flags affect the general behavior of the compiler.
   The supported flags are:
 
   * 1995
-    
+
     This flag enables the IEEE1364-1995 standard.
 
   * 2001
-    
+
     This flag enables the IEEE1364-2001 standard.
 
   * 2001-noconfig
-    
+
     This flag enables the IEEE1364-2001 standard with config file support
     disabled. This eliminates the config file keywords from the language and
     so helps some programs written to older 2001 support compile.
@@ -64,17 +64,17 @@ These flags affect the general behavior of the compiler.
     support is ongoing.
 
   * 2012
-    
+
     This flag enables the IEEE1800-2012 standard, which includes
     SystemVerilog.
 
   * verilog-ams
-    
+
     This flag enables Verilog-AMS features that are supported by Icarus
     Verilog. (This is new as of 5 May 2008.)
 
   * assertions/supported-assertions/no-assertions
-    
+
     Enable or disable SystemVerilog assertions. When enabled, assertion
     statements are elaborated. When disabled, assertion statements are parsed
     but ignored. The supported-assertions option only enables assertions that
@@ -278,7 +278,7 @@ These flags affect the general behavior of the compiler.
     will print a warning at its first use.
 
   * implicit-dimensions
-    
+
     This enables warnings for the case where a port declaration or a var/net
     declaration for the same name is missing dimensions. Normally, Verilog
     allows you to do this (the undecorated declaration gets its dimensions
@@ -289,40 +289,40 @@ These flags affect the general behavior of the compiler.
     2016-02-06.
 
   * macro-redefinition
-    
+
     This enables warnings when a macro is redefined, even if the macro text
     remains the same.
 
     NOTE: The "macro-redefinition" flag was added in v11.0.
 
   * macro-replacement
-    
+
     This enables warnings when a macro is redefined and the macro text
     changes. Use no-macro-redefinition to disable this,
 
     NOTE: The "macro-replacement" flag was added in v11.0.
 
   * portbind
-    
+
     This enables warnings for ports of module instantiations that are not
     connected properly, but probably should be. Dangling input ports, for
     example, will generate a warning.
 
   * select-range
-    
+
     This enables warnings for constant out-of-bound selects. This includes
     partial or fully out-of-bound select as well as a select containing a 'bx
     or 'bz in the index.
 
   * timescale
-    
+
     This enables warnings for inconsistent use of the timescale directive. It
     detects if some modules have no timescale, or if modules inherit timescale
     from another file. Both probably mean that timescales are inconsistent,
     and simulation timing can be confusing and dependent on compilation order.
 
   * infloop
-    
+
     This enables warnings for always statements that may have runtime infinite
     loops (i.e. has paths with zero or no delay). This class of warnings is
     not included in -Wall and hence does not have a no- variant. A fatal error
@@ -352,7 +352,7 @@ These flags affect the general behavior of the compiler.
     is large.
 
   * floating-nets
-    
+
     This enables warnings for nets that are present but have no drivers.
 
     This flag was added in version 11.0 or later (and is in the master branch
@@ -389,7 +389,7 @@ flags for the typical "C" compiler, so C programmers will find them familiar.
   for other tools. For example, this command::
 
     % iverilog -E -ofoo.v -DKEY=10 src1.v src2.v
-    
+
   runs the preprocessor on the source files src1.v and src2.v and produces the
   single output file foo.v that has all the preprocessing (including header
   includes and ifdefs) processed.
@@ -421,7 +421,7 @@ Elaboration Flags
 These are flags that pass information to the elaboration steps.
 
 * -P<symbol>=<value>
-  
+
   Define a parameter using the defparam behavior to override a parameter
   values. This can only be used for parameters of root module instances.
 

Documentation/usage/getting_started.rst

@@ -23,7 +23,7 @@ World program.
 .. code-block:: verilog
 
   module hello;
-    initial 
+    initial
       begin
         $display("Hello, World");
         $finish ;
@@ -70,10 +70,10 @@ example, the counter model in counter.v
     parameter WIDTH = 8;
 
     output [WIDTH-1 : 0] out;
-    input 	       clk, reset;
+    input	       clk, reset;
 
     reg [WIDTH-1 : 0]   out;
-    wire 	       clk, reset;
+    wire	       clk, reset;
 
     always @(posedge clk or posedge reset)
       if (reset)

Documentation/usage/installation.rst

@@ -22,8 +22,8 @@ specific branch. Stable releases are placed on branches, and in particular v11
 stable releases are on the branch "v11-branch" To get the development version
 of the code follow these steps::
 
-  % git config --global user.name "Your Name Goes Here"   
-  % git config --global user.email you@yourpublicemail.example.com   
+  % git config --global user.name "Your Name Goes Here"
+  % git config --global user.email you@yourpublicemail.example.com
   % git clone https://github.com/steveicarus/iverilog.git
 
 The first two lines are optional and are used to tell git who you are. This
@@ -69,9 +69,9 @@ build instructions below for your operation system for what to do next.
 You will need autoconf and gperf installed in order for the script to work.
 If you get errors such as::
 
-  Autoconf in root...   
-  autoconf.sh: 10: autoconf: not found   
-  Precompiling lexor_keyword.gperf  
+  Autoconf in root...
+  autoconf.sh: 10: autoconf: not found
+  Precompiling lexor_keyword.gperf
   autoconf.sh: 13: gperf: not found.
 
 You will need to install download and install the autoconf and gperf tools.
@@ -108,9 +108,9 @@ Compiling on Linux/Unix
 easiest case. Given that you have the source tree from the above instructions,
 the compile and install is generally as simple as::
 
-  % ./configure  
-  % make  
-  (su to root)  
+  % ./configure
+  % make
+  (su to root)
   # make install
 
 The "make install" typically needs to be done as root so that it can install

Documentation/usage/simulation.rst

@@ -295,8 +295,8 @@ Consider this running example of a square root calculator
           bitl = 15;
        end
     endtask
-  
-    initial clear;   
+
+    initial clear;
 
     always @(reset or posedge clk)
        if (reset)
@@ -373,7 +373,7 @@ be modified as follows
   module main;
 
     reg clk, reset;
-    reg  [31:0] x; 
+    reg  [31:0] x;
     reg  [31:0] z;
     wire [15:0] y1,y2;
     wire        rdy1,rdy2;

Documentation/usage/verilog_attributes.rst

@@ -13,7 +13,7 @@ Optimizations
 -------------
 
 * ivl_do_not_elide (snapshot 20140619 or later)
-  
+
   This applies to signals (i.e. reg, wire, etc.) and tells the optimizer to
   not elide the signal, even if it is not referenced anywhere in the
   design. This is useful if the signal is for some reason only accessed by
@@ -23,13 +23,13 @@ Synthesis
 ---------
 
 * ivl_synthesis_cell
-  
+
   Applied to a module definition, this tells the synthesizer that the module
   is a cell. The synthesizer does not descend into synthesis cells, as they
   are assumed to be primitives in the target technology.
 
 * ivl_synthesis_off
-  
+
   Attached to an "always" statement, this tells the synthesizer that the
   statement is not to be synthesized. This may be useful, for example, to tell
   the compiler that a stretch of code is test-bench code.

Documentation/usage/vvp_debug.rst

@@ -78,7 +78,7 @@ terminal interrupt and drops you into the interactive prompt::
   ^C** VVP Stop(0) **
   ** Flushing output streams.
   ** Current simulation time is 533928600 ticks.
-  > 
+  >
 
 This could be useful if you suspect that your simulation is stuck in
 an infinite loop and you want to rummage around and see what's going on.

Documentation/usage/vvp_flags.rst

@@ -73,12 +73,12 @@ behavior.
   synonyms for turning of dumping.
 
 * -fst
-  
+
   Generate FST format outputs instead of VCD format waveform dumps. This is
   the preferred output format if using GTKWave for viewing waveforms.
 
 * -lxt/-lxt2
-  
+
   Generate LXT or LXT2format instead of VCD format waveform dumps. The LXT2
   format is more advanced.
 
@@ -96,15 +96,15 @@ The Icarus Verilog support for SDF back-annotation can take some extended
 arguments to control aspects of SDF support.
 
 * -sdf-warn
-  
+
   Print warnings during load of/annotation from an SDF file.
 
 * -sdf-info
-  
+
   Print interesting information about an SDF file while parsing it.
 
 * -sdf-verbose
-  
+
   Print warnings and info messages.
 
 Environment Variables

README.md

@@ -393,7 +393,7 @@ more details.
 	the same thing, but included in the SystemVerilog definition.
 
 * `$simtime`
-	
+
   The `$simtime` system function returns as a 64bit value the
 	simulation time, unscaled by the time units of local
 	scope. This is different from the $time and $stime functions

elaborate.cc

@@ -5542,7 +5542,7 @@ NetProc* PForStatement::elaborate(Design*des, NetScope*scope) const
 		  des->errors += 1;
 		  return 0;
 	    }
-	    
+
 	    // Make the r-value of the initial assignment, and size it
 	    // properly. Then use it to build the assignment statement.
 	    initial_expr = elaborate_rval_expr(des, scope, sig->net_type(),

ivtest/ivltests/br_gh156.v

@@ -13,7 +13,7 @@ module main;
       $dumpfile("work/br_gh156.vcd");
       $dumpvars(0, main);
       #1 $finish;
-      
+
    end
-   
+
 endmodule // main

ivtest/ivltests/br_gh191_break.v

@@ -12,7 +12,7 @@ module main;
 	 $display("FAILED -- break from for loop");
 	 $finish;
       end
-      
+
       idx = 0;
       forever begin
 	 idx += 1;

ivtest/ivltests/br_gh540.v

@@ -60,5 +60,5 @@ initial begin
   else
     $display("PASSED");
 end
-  
+
 endmodule

ivtest/ivltests/br_gh788.v

@@ -8,11 +8,11 @@ task print_hex;
 
   begin
     $display("%h", n);
-  end  
+  end
 endtask
 
 initial begin
   print_hex(66);
 end
-   
+
 endmodule

ivtest/ivltests/dumpfile.v

@@ -9,7 +9,7 @@ module main;
       #10 clk <= 1;
       #10 clk <= 0;
       #10 $finish;
-      
+
    end
 
 endmodule // main

ivtest/ivltests/func_empty_arg_fail3.v

@@ -9,7 +9,7 @@ module test;
 
   initial begin
     integer x;
-    x = f( , ); // This should fail. The function takes no arguments. 
+    x = f( , ); // This should fail. The function takes no arguments.
     $display("FAILED");
   end
 

ivtest/ivltests/issue576.v

@@ -11,5 +11,5 @@ module test;
    endfunction // fun
 
    always_comb fun;
-   
+
 endmodule

ivtest/ivltests/sdf_header.sdf

@@ -10,7 +10,7 @@
   (PROCESS "best=0.65:nom=1.0:worst=1.8")
   (TEMPERATURE -25.0:25.0:85.0)
   (TIMESCALE 1 ps)
-  
+
   // Do nothing
   (CELL
         (CELLTYPE "top")

ivtest/ivltests/sv_string6.v

@@ -2,9 +2,9 @@
 
 module testbench;
    string str;
-   int 	  val;
+   int	  val;
    real   valr;
-   
+
 
    task test_string_value(string str, string reference);
       if (str != reference) begin
@@ -12,7 +12,7 @@ module testbench;
 	 $finish;
       end
    endtask // test_string_value
-   
+
    initial begin
       val = 11;
       valr = 11.1;
@@ -51,6 +51,6 @@ module testbench;
       test_string_value(str, "-11.1");
 
       $display("PASSED");
-      
+
    end
 endmodule

ivtest/ivltests/sv_string7.v

@@ -2,7 +2,7 @@
 module main;
 
    string foo;
-   int 	  error_count;
+   int	  error_count;
 
    task check_char(input int idx, input [7:0] val);
       if (foo[idx] !== val) begin
@@ -11,7 +11,7 @@ module main;
 	 error_count = error_count+1;
       end
    endtask // check_char
-   
+
    initial begin
       // These are the special charasters in strings as defined by
       // IEEE Std 1800-2017: 5.9.1 Special characters in strings.

ivtest/ivltests/sv_string7b.v

@@ -2,7 +2,7 @@
 module main;
 
    string foo;
-   int 	  error_count;
+   int	  error_count;
 
    task check_char(input int idx, input [7:0] val);
       if (foo[idx] !== val) begin
@@ -11,7 +11,7 @@ module main;
 	 error_count = error_count+1;
       end
    endtask // check_char
-   
+
    initial begin
       // These are the special charasters in strings as defined by
       // IEEE Std 1800-2017: 5.9.1 Special characters in strings.

ivtest/regress-sv.list

@@ -755,8 +755,8 @@ sv_ps_member_sel2	normal,-g2009		ivltests
 sv_ps_member_sel3	normal,-g2009		ivltests
 sv_ps_method1		normal,-g2009		ivltests
 sv_ps_method2		normal,-g2009		ivltests
-sv_ps_method3	  	normal,-g2009		ivltests
-sv_ps_method4	  	normal,-g2009		ivltests
+sv_ps_method3		normal,-g2009		ivltests
+sv_ps_method4		normal,-g2009		ivltests
 sv_ps_type1		normal,-g2009		ivltests
 sv_ps_type_cast1	normal,-g2009		ivltests
 sv_ps_type_cast2	normal,-g2009		ivltests

ivtest/regress-vlg.list

@@ -1516,8 +1516,8 @@ real_reg_force_rel	normal			ivltests
 recursive_func1		normal			ivltests gold=recursive_func.gold
 recursive_func_const1	normal			ivltests gold=recursive_func_const.gold
 recursive_task		normal			ivltests gold=recursive_task.gold
-redef_net_error 	CE			ivltests
-redef_reg_error 	CE			ivltests
+redef_net_error		CE			ivltests
+redef_reg_error		CE			ivltests
 repeat2			normal			ivltests
 repeat_expr_probe	normal			ivltests
 repl_zero_wid_fail	CE			ivltests

ivtest/run_ivl.py

@@ -131,7 +131,7 @@ def run_CE(options : dict) -> list:
 
 def check_run_outputs(options : dict, expected_fail : bool, it_stdout : str, log_list : list) -> list:
     '''Check the output files, and return success for failed.
-    
+
     This function takes an options dictionary that describes the settings, and
     the output from the final command. This also takes a list of log files to check
     there there are gold files present.'''
@@ -240,7 +240,7 @@ def do_run_normal_vlog95(options : dict, expected_fail : bool) -> list:
     vvp_cmd = assemble_vvp_cmd(it_vvp_args, it_vvp_args_extended)
     vvp_res = subprocess.run(vvp_cmd, capture_output=True)
     log_results(it_key, "vvp", vvp_res);
-        
+
     if vvp_res.returncode != 0:
         return [1, "Failed - Vvp execution failed"]
 
@@ -279,7 +279,7 @@ def do_run_normal(options : dict, expected_fail : bool) -> list:
     vvp_cmd = assemble_vvp_cmd(it_vvp_args, it_vvp_args_extended)
     vvp_res = subprocess.run(vvp_cmd, capture_output=True)
     log_results(it_key, "vvp", vvp_res);
-        
+
     if vvp_res.returncode != 0:
         return [1, "Failed - Vvp execution failed"]
 

ivtest/test_lists.py

@@ -72,5 +72,5 @@ def read_lists(paths: list) -> list:
     # Convert the result to a sorted list, and return that.
     tests_list = list(tests_dict.values())
     tests_list.sort()
-    
+
     return tests_list

ivtest/vvp_reg.py

@@ -93,7 +93,7 @@ if __name__ == "__main__":
     if len(list_paths) == 0:
         list_paths = list()
         list_paths += ["regress-vvp.list"]
-        
+
     print(f"Use lists: {list_paths}")
 
     # Read the list files, to get the tests.
@@ -115,4 +115,4 @@ if __name__ == "__main__":
     print("===================================================")
     print(f"Test results: Ran {len(tests_list)}, Failed {error_count}.")
     exit(error_count)
-    
+

t-dll-proc.cc

@@ -780,7 +780,7 @@ bool dll_target::proc_forloop(const NetForLoop*net)
       save_cur_->u_.forloop_.condition = expr_;
       expr_ = nullptr;
       res = res && rc;
-      
+
       stmt_cur_ = save_cur_;
       return res;
 }

tgt-vvp/vvp_proc_loops.c

@@ -217,6 +217,6 @@ int show_stmt_while(ivl_statement_t net, ivl_scope_t sscope)
       fprintf(vvp_out, "T_%u.%u ;\n", thread_count, out_label);
 
       POP_JUMPS;
-      
+
       return rc;
 }