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Remove the .word statement.

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steve 2005-07-13 04:58:29 +00:00
parent 5bfdd52391
commit 559a1fd359
1 changed files with 1 additions and 16 deletions
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17
vvp/README.txt
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@ -1,7 +1,7 @@
/*
* Copyright (c) 2001 Stephen Williams (steve@icarus.com)
*
* $Id: README.txt,v 1.69 2005/07/06 04:29:25 steve Exp $
* $Id: README.txt,v 1.70 2005/07/13 04:58:29 steve Exp $
*/
VVP SIMULATION ENGINE
@ -422,21 +422,6 @@ to trigger this event. Only one of the input events needs to trigger
to make this one go.
WORD STATEMENTS (deprecated):
Verilog includes some scalar word types available to the programmer,
including real variables, and possible extension types that the code
generator can transparently use. Variables of these special types are
declared with .word statements:
<label> .word <type>, "vpi name";
The <type> values supported are listed below. The vpi name is the base
name given to the VPI object that is created.
real - represents a double precision real variable.
RESOLVER STATEMENTS:
Resolver statements are strength-aware functors with 4 inputs, but