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Assert that sync/async set/clear are not supported for a DFF primitive. 

Since synthesis is not currently supported we do not support/generate
sync/async set or clear control inputs. This is further complicated by
the fact that the VVP DFF primitive is not fully implemented.
This commit is contained in:
Cary R 2011-11-11 17:52:01 -08:00 committed by Stephen Williams
parent bcb963a235
commit 36d298a2b6
1 changed files with 21 additions and 27 deletions
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48
tgt-vvp/vvp_scope.c
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@ -1622,51 +1622,45 @@ static void draw_lpm_concat(ivl_lpm_t net)
}
/*
* primitive FD (q, clk, ce, d);
* output q;
* reg q;
* input clk, ce, d;
* table
* // clk ce d r s q q+
* r 1 0 0 0 : ? : 0;
* r 1 1 0 0 : ? : 1;
* f 1 ? 0 0 : ? : -;
* ? 1 ? 0 0 : ? : -;
* * 0 ? 0 0 : ? : -;
* ? ? ? 1 ? : ? : 0;
* ? ? ? 0 1 : ? : 1;
* endtable
* endprimitive
* Emit a DFF primitive. This uses the following syntax:
*
* .dff <data>, <clock>, <enable>, <async>;
*
* The async pin currently sets the stored data value and propagates it
* to the output (not very useful). This routine always sets the async
* value to high-Z which is ignored in the VVP code. This is all OK
* since synthesis is not currently functional.
*/
static void draw_lpm_ff(ivl_lpm_t net)
{
ivl_expr_t aset_expr = 0;
const char*aset_bits = 0;
ivl_nexus_t nex;
unsigned width;
width = ivl_lpm_width(net);
aset_expr = ivl_lpm_aset_value(net);
if (aset_expr) {
assert(ivl_expr_width(aset_expr) == width);
aset_bits = ivl_expr_bits(aset_expr);
}
/* Sync/Async set/clear control is currently only supported in V0.8
* which has working synthesis. If/when this is added see that code
* for clues about how this should be implemented. The dff primitive
* used here (from vvp) needs to be improved to support both an
* async set and clear. See the UDP generated by the tgt-vlog95 code
* generator in V0.10 and later for how this might be done. */
assert(ivl_lpm_sync_clr(net) == 0);
assert(ivl_lpm_sync_set(net) == 0);
assert(ivl_lpm_async_clr(net) == 0);
assert(ivl_lpm_async_set(net) == 0);
fprintf(vvp_out, "L_%p .dff ", net);
nex = ivl_lpm_data(net,0);
assert(nex);
fprintf(vvp_out, "%s", draw_net_input(nex));
assert(width_of_nexus(nex) == ivl_lpm_width(net));;
nex = ivl_lpm_clk(net);
assert(nex);
assert(width_of_nexus(nex) == 1);;
fprintf(vvp_out, ", %s", draw_net_input(nex));
nex = ivl_lpm_enable(net);
if (nex) {
assert(width_of_nexus(nex) == 1);;
fprintf(vvp_out, ", %s", draw_net_input(nex));
} else {
fprintf(vvp_out, ", C4<1>");