Store only a single VHDL entity for each Verilog module

tgt-vhdl/expr.cc

@@ -511,7 +511,7 @@ static vhdl_expr *translate_ufunc(ivl_expr_t e)
    // A function is always declared in a module, which should have
    // a corresponding entity by this point: so we can get type
    // information, etc. from the declaration
-   vhdl_entity *parent_ent = find_entity(ivl_scope_name(parentscope));
+   vhdl_entity *parent_ent = find_entity(parentscope);
    assert(parent_ent);
 
    const char *funcname = ivl_scope_tname(defscope);

tgt-vhdl/process.cc

@@ -98,7 +98,7 @@ int draw_process(ivl_process_t proc, void *cd)
    // A process should occur in a module scope, therefore it
    // should have already been assigned a VHDL entity
    assert(ivl_scope_type(scope) == IVL_SCT_MODULE);
-   vhdl_entity *ent = find_entity(ivl_scope_name(scope));
+   vhdl_entity *ent = find_entity(scope);
    assert(ent != NULL);
    
    return generate_vhdl_process(ent, proc);

tgt-vhdl/scope.cc

@@ -243,7 +243,7 @@ void draw_nexus(ivl_nexus_t nexus)
          if (!is_default_scope_instance(log_scope))
             continue;
          
-         vhdl_entity *ent = find_entity(ivl_scope_name(log_scope));
+         vhdl_entity *ent = find_entity(log_scope);
          assert(ent);
          
          vhdl_scope *vhdl_scope = ent->get_arch()->get_scope();
@@ -269,7 +269,7 @@ void draw_nexus(ivl_nexus_t nexus)
       }
       else if ((lpm = ivl_nexus_ptr_lpm(nexus_ptr))) {
          ivl_scope_t lpm_scope = ivl_lpm_scope(lpm);
-         vhdl_entity *ent = find_entity(ivl_scope_name(lpm_scope));
+         vhdl_entity *ent = find_entity(lpm_scope);
          assert(ent);
          
          vhdl_scope *vhdl_scope = ent->get_arch()->get_scope();
@@ -610,10 +610,10 @@ static void map_signal(ivl_signal_t to, vhdl_entity *parent,
       pdecl->set_mode(VHDL_PORT_BUFFER);
 
       // Now change the mode in the child entity
-      vhdl_port_decl *to_pdecl =
+      /*      vhdl_port_decl *to_pdecl =
          dynamic_cast<vhdl_port_decl*>(find_scope_for_signal(to)->get_decl(name));
       assert(to_pdecl);
-      to_pdecl->set_mode(VHDL_PORT_BUFFER);
+      to_pdecl->set_mode(VHDL_PORT_BUFFER);*/
    }
    
    inst->map_port(name.c_str(), ref);
@@ -657,7 +657,7 @@ static int draw_function(ivl_scope_t scope, ivl_scope_t parent)
              ivl_scope_name(scope));
 
    // Find the containing entity
-   vhdl_entity *ent = find_entity(ivl_scope_name(parent));
+   vhdl_entity *ent = find_entity(parent);
    assert(ent);
 
    const char *funcname = ivl_scope_tname(scope);
@@ -734,7 +734,7 @@ static int draw_task(ivl_scope_t scope, ivl_scope_t parent)
    assert(ivl_scope_type(scope) == IVL_SCT_TASK);
 
    // Find the containing entity
-   vhdl_entity *ent = find_entity(ivl_scope_name(parent));
+   vhdl_entity *ent = find_entity(parent);
    assert(ent);
 
    const char *taskname = ivl_scope_tname(scope);
@@ -778,18 +778,14 @@ static void create_skeleton_entity_for(ivl_scope_t scope, int depth)
    assert(ivl_scope_type(scope) == IVL_SCT_MODULE);
 
    // The type name will become the entity name
-   const char *tname = ivl_scope_tname(scope);
-
-   // Remember the scope name this entity was derived from so
-   // the correct processes can be added later
-   const char *derived_from = ivl_scope_name(scope);
+   const char *tname = ivl_scope_tname(scope);;
    
    // Verilog does not have the entity/architecture distinction
    // so we always create a pair and associate the architecture
    // with the entity for convenience (this also means that we
    // retain a 1-to-1 mapping of scope to VHDL element)
    vhdl_arch *arch = new vhdl_arch(tname, "FromVerilog");
-   vhdl_entity *ent = new vhdl_entity(tname, derived_from, arch, depth);
+   vhdl_entity *ent = new vhdl_entity(tname, arch, depth);
 
    // Build a comment to add to the entity/architecture
    ostringstream ss;
@@ -812,7 +808,7 @@ static int draw_skeleton_scope(ivl_scope_t scope, void *_unused)
    static int depth = 0;
    
    if (seen_this_scope_type(scope)) {
-      debug_msg("Ignoring scope: %s\n", ivl_scope_name(scope));
+      debug_msg("Ignoring scope: %s", ivl_scope_name(scope));
       return 0;
    }
    
@@ -848,7 +844,7 @@ static int draw_all_signals(ivl_scope_t scope, void *_parent)
    }
    
    if (ivl_scope_type(scope) == IVL_SCT_MODULE) {
-      vhdl_entity *ent = find_entity(ivl_scope_name(scope));
+      vhdl_entity *ent = find_entity(scope);
       assert(ent);
 
       declare_signals(ent, scope);
@@ -897,7 +893,7 @@ static int draw_constant_drivers(ivl_scope_t scope, void *_parent)
    ivl_scope_children(scope, draw_constant_drivers, scope);
    
    if (ivl_scope_type(scope) == IVL_SCT_MODULE) {
-      vhdl_entity *ent = find_entity(ivl_scope_name(scope));
+      vhdl_entity *ent = find_entity(scope);
       assert(ent);
 
       int nsigs = ivl_scope_sigs(scope);
@@ -956,7 +952,7 @@ static int draw_all_logic_and_lpm(ivl_scope_t scope, void *_parent)
    
    
    if (ivl_scope_type(scope) == IVL_SCT_MODULE) {
-      vhdl_entity *ent = find_entity(ivl_scope_name(scope));
+      vhdl_entity *ent = find_entity(scope);
       assert(ent);
 
       set_active_entity(ent);
@@ -980,10 +976,10 @@ static int draw_hierarchy(ivl_scope_t scope, void *_parent)
          return 0;
       }   
    
-      vhdl_entity *ent = find_entity(ivl_scope_name(scope));
+      vhdl_entity *ent = find_entity(scope);
       assert(ent);
       
-      vhdl_entity *parent_ent = find_entity(ivl_scope_name(parent));
+      vhdl_entity *parent_ent = find_entity(parent);
       assert(parent_ent);
 
       vhdl_arch *parent_arch = parent_ent->get_arch();

tgt-vhdl/vhdl.cc

@@ -32,6 +32,7 @@
 #include <list>
 #include <map>
 #include <set>
+#include <algorithm>
 
 static const char*version_string =
 "Icarus Verilog VHDL Code Generator " VERSION " (" VERSION_TAG ")\n\n"
@@ -106,26 +107,42 @@ void debug_msg(const char *fmt, ...)
    va_end(args);
 }
 
-/*
- * Find an entity given a scope name.
- */
-vhdl_entity *find_entity(const std::string &sname)
-{
-   entity_list_t::const_iterator it;
-   for (it = g_entities.begin(); it != g_entities.end(); ++it) {
-      if ((*it)->get_derived_from() == sname)
-         return *it;
+// Compare the name of an entity against a string
+struct cmp_ent_name {
+   cmp_ent_name(const string& n) : name_(n) {}
+   
+   bool operator()(const vhdl_entity* ent) const
+   {
+      return ent->get_name() == name_;
    }
-   return NULL;
+
+   const string& name_;
+};
+
+/*
+ * Find a VHDL entity given a Verilog module scope. The VHDL entity
+ * name should be the same the Verilog module type name.
+ */
+vhdl_entity *find_entity(const ivl_scope_t scope)
+{
+   debug_msg("find_entity %s", ivl_scope_tname(scope));
+   assert(ivl_scope_type(scope) == IVL_SCT_MODULE);
+
+   entity_list_t::const_iterator it
+      = find_if(g_entities.begin(), g_entities.end(),
+                cmp_ent_name(ivl_scope_tname(scope)));
+
+   if (it != g_entities.end())
+      return *it;
+   else
+      return NULL;
 }
 
 /*
- * Add an entity/architecture pair to the list of entities
- * to emit.
+ * Add an entity/architecture pair to the list of entities to emit.
  */
 void remember_entity(vhdl_entity* ent)
 {
-   assert(find_entity(ent->get_derived_from()) == NULL);
    g_entities.push_back(ent);
 }
 

tgt-vhdl/vhdl_syntax.cc

@@ -87,9 +87,8 @@ vhdl_scope *vhdl_scope::get_parent() const
    return parent_;
 }
 
-vhdl_entity::vhdl_entity(const char *name, const char *derived_from,
-                         vhdl_arch *arch, int depth__)
-   :  depth(depth__), name_(name), arch_(arch), derived_from_(derived_from)
+vhdl_entity::vhdl_entity(const char *name, vhdl_arch *arch, int depth__)
+   :  depth(depth__), name_(name), arch_(arch)
 {
    arch->get_scope()->set_parent(&ports_);
 }

tgt-vhdl/vhdl_syntax.hh

@@ -807,15 +807,13 @@ private:
  */
 class vhdl_entity : public vhdl_element {
 public:
-   vhdl_entity(const char *name, const char *derived_from,
-               vhdl_arch *arch, int depth=0);
+   vhdl_entity(const char *name, vhdl_arch *arch, int depth=0);
    virtual ~vhdl_entity();
 
    void emit(std::ostream &of, int level=0) const;
    void add_port(vhdl_port_decl *decl);
    vhdl_arch *get_arch() const { return arch_; }
    const std::string &get_name() const { return name_; }
-   const std::string &get_derived_from() const { return derived_from_; }
 
    vhdl_scope *get_scope() { return &ports_; }
    
@@ -826,7 +824,6 @@ public:
 private:
    std::string name_;
    vhdl_arch *arch_;  // Entity may only have a single architecture
-   std::string derived_from_;
    vhdl_scope ports_;
 };
 

tgt-vhdl/vhdl_target.h

@@ -27,7 +27,7 @@ vhdl_expr *translate_expr(ivl_expr_t e);
 vhdl_expr *translate_time_expr(ivl_expr_t e);
 
 void remember_entity(vhdl_entity *ent);
-vhdl_entity *find_entity(const string &sname);
+vhdl_entity *find_entity(const ivl_scope_t scope);
 
 ivl_design_t get_vhdl_design();
 vhdl_entity *get_active_entity();