Make sure signal names conform to VHDL rules
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@ -140,19 +140,24 @@ static void declare_signals(vhdl_arch *arch, ivl_scope_t scope)
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remember_signal(sig, arch->get_parent());
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const char *name = ivl_signal_basename(sig);
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// Make sure the signal name conforms to VHDL naming rules
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std::string name(ivl_signal_basename(sig));
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if (name[0] == '_')
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name.insert(0, "VL");
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rename_signal(sig, name.c_str());
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ivl_signal_port_t mode = ivl_signal_port(sig);
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switch (mode) {
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case IVL_SIP_NONE:
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arch->add_decl(new vhdl_signal_decl(name, sig_type));
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arch->add_decl(new vhdl_signal_decl(name.c_str(), sig_type));
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break;
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case IVL_SIP_INPUT:
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arch->get_parent()->add_port
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(new vhdl_port_decl(name, sig_type, VHDL_PORT_IN));
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(new vhdl_port_decl(name.c_str(), sig_type, VHDL_PORT_IN));
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break;
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case IVL_SIP_OUTPUT:
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arch->get_parent()->add_port
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(new vhdl_port_decl(name, sig_type, VHDL_PORT_OUT));
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(new vhdl_port_decl(name.c_str(), sig_type, VHDL_PORT_OUT));
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if (ivl_signal_type(sig) == IVL_SIT_REG) {
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// A registered output
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@ -165,19 +170,19 @@ static void declare_signals(vhdl_arch *arch, ivl_scope_t scope)
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rename_signal(sig, newname.c_str());
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vhdl_type *reg_type = new vhdl_type(*sig_type);
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arch->add_decl(new vhdl_signal_decl(newname.c_str(), reg_type));
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arch->add_decl(new vhdl_signal_decl(newname.c_str(), reg_type));
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// Create a concurrent assignment statement to
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// connect the register to the output
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arch->add_stmt
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(new vhdl_cassign_stmt
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(new vhdl_var_ref(name, NULL),
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(new vhdl_var_ref(name.c_str(), NULL),
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new vhdl_var_ref(newname.c_str(), NULL)));
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}
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break;
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case IVL_SIP_INOUT:
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arch->get_parent()->add_port
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(new vhdl_port_decl(name, sig_type, VHDL_PORT_INOUT));
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(new vhdl_port_decl(name.c_str(), sig_type, VHDL_PORT_INOUT));
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break;
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}
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}
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