Refactor task declaration parsing and fix warning for empty port list.
1364-2005 and later allow a task declaration with an empty port list.
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c4883da334
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46
parse.y
46
parse.y
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@ -2321,7 +2321,7 @@ task_declaration /* IEEE1800-2005: A.2.7 */
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{ assert(current_task == 0);
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current_task = pform_push_task_scope(@1, $3, $2);
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}
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tf_port_list ')' ';'
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tf_port_list_opt ')' ';'
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block_item_decls_opt
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statement_or_null_list_opt
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K_endtask
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@ -2329,6 +2329,10 @@ task_declaration /* IEEE1800-2005: A.2.7 */
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current_task_set_statement(@3, $10);
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pform_set_this_class(@3, current_task);
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pform_pop_scope();
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if (generation_flag < GN_VER2005 && $6 == 0) {
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cerr << @3 << ": warning: task definition for \"" << $3
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<< "\" has an empty port declaration list!" << endl;
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}
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current_task = 0;
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if ($10) delete $10;
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}
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@ -2351,46 +2355,6 @@ task_declaration /* IEEE1800-2005: A.2.7 */
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delete[]$3;
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}
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| K_task lifetime_opt IDENTIFIER '(' ')' ';'
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{ assert(current_task == 0);
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current_task = pform_push_task_scope(@1, $3, $2);
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}
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block_item_decls_opt
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statement_or_null_list
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K_endtask
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{ current_task->set_ports(0);
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current_task_set_statement(@3, $9);
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pform_set_this_class(@3, current_task);
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if (! current_task->method_of()) {
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cerr << @3 << ": warning: task definition for \"" << $3
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<< "\" has an empty port declaration list!" << endl;
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}
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pform_pop_scope();
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current_task = 0;
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if ($9->size() > 1 && !gn_system_verilog()) {
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yyerror(@9, "error: Task body with multiple statements requires SystemVerilog.");
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}
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delete $9;
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}
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endlabel_opt
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{ // Last step: check any closing name. This is done late so
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// that the parser can look ahead to detect the present
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// endlabel_opt but still have the pform_endmodule() called
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// early enough that the lexor can know we are outside the
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// module.
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if ($12) {
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if (strcmp($3,$12) != 0) {
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yyerror(@12, "error: End label doesn't match task name");
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}
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if (! gn_system_verilog()) {
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yyerror(@12, "error: Task end labels require "
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"SystemVerilog.");
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}
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delete[]$12;
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}
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delete[]$3;
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}
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| K_task lifetime_opt IDENTIFIER error K_endtask
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{
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if (current_task) {
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