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Add new %cast/vec4/str instruction to vvp.

This commit is contained in:
Martin Whitaker 2019-09-09 21:39:35 +01:00
parent 34bb98676a
commit 74ff44314e
4 changed files with 45 additions and 4 deletions
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3
vvp/codes.h
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@ -1,7 +1,7 @@
#ifndef IVL_codes_H
#define IVL_codes_H
/*
* Copyright (c) 2001-2017 Stephen Williams (steve@icarus.com)
* Copyright (c) 2001-2019 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@ -66,6 +66,7 @@ extern bool of_CASSIGN_VEC4(vthread_t thr, vvp_code_t code);
extern bool of_CASSIGN_VEC4_OFF(vthread_t thr, vvp_code_t code);
extern bool of_CASSIGN_WR(vthread_t thr, vvp_code_t code);
extern bool of_CAST2(vthread_t thr, vvp_code_t code);
extern bool of_CAST_VEC4_STR(vthread_t thr, vvp_code_t code);
extern bool of_CMPE(vthread_t thr, vvp_code_t code);
extern bool of_CMPIE(vthread_t thr, vvp_code_t code);
extern bool of_CMPINE(vthread_t thr, vvp_code_t code);

3
vvp/compile.cc
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2001-2018 Stephen Williams (steve@icarus.com)
* Copyright (c) 2001-2019 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@ -117,6 +117,7 @@ static const struct opcode_table_s opcode_table[] = {
{ "%cassign/vec4", of_CASSIGN_VEC4, 1,{OA_FUNC_PTR,OA_NONE, OA_NONE} },
{ "%cassign/vec4/off",of_CASSIGN_VEC4_OFF,2,{OA_FUNC_PTR,OA_BIT1, OA_NONE} },
{ "%cassign/wr", of_CASSIGN_WR, 1,{OA_FUNC_PTR,OA_NONE, OA_NONE} },
{ "%cast/vec4/str", of_CAST_VEC4_STR, 1, {OA_NUMBER, OA_NONE, OA_NONE} },
{ "%cast2", of_CAST2, 0, {OA_NONE, OA_NONE, OA_NONE} },
{ "%cmp/e", of_CMPE, 0, {OA_NONE, OA_NONE, OA_NONE} },
{ "%cmp/ne", of_CMPNE, 0, {OA_NONE, OA_NONE, OA_NONE} },

8
vvp/opcodes.txt
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2001-2017 Stephen Williams (steve@icarus.com)
* Copyright (c) 2001-2019 Stephen Williams (steve@icarus.com)
*
*/
@ -258,6 +258,12 @@ value stack.
Pop a value from the vec4 stack, convert it using Verilog rules to a
vector2 (binary) value, and push the result.
* %cast/vec4/str <wid>
Pop a value from the string stack, convert it to a vector that is <wid>
bits wide, and push the result to the vec4 stack. If the string does not
fit exactly in <wid> bits, print an error message and stop the simulation.
* %cmp/s
* %cmp/u
* %cmp/e

35
vvp/vthread.cc
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2001-2018 Stephen Williams (steve@icarus.com)
* Copyright (c) 2001-2019 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@ -1547,6 +1547,39 @@ bool of_CAST2(vthread_t thr, vvp_code_t)
return true;
}
/*
* %cast/vec4/str <wid>
*/
bool of_CAST_VEC4_STR(vthread_t thr, vvp_code_t cp)
{
unsigned wid = cp->number;
string str = thr->pop_str();
vvp_vector4_t vec(wid, BIT4_0);
if (wid != 8*str.length()) {
cerr << "VVP error: size mismatch when casting string to vector." << endl;
thr->push_vec4(vec);
schedule_stop(0);
return false;
}
unsigned sdx = 0;
unsigned vdx = wid;
while (vdx > 0) {
char ch = str[sdx++];
vdx -= 8;
for (unsigned bdx = 0; bdx < 8; bdx += 1) {
if (ch & 1)
vec.set_bit(vdx+bdx, BIT4_1);
ch >>= 1;
}
}
thr->push_vec4(vec);
return true;
}
static void do_CMPE(vthread_t thr, const vvp_vector4_t&lval, const vvp_vector4_t&rval)
{
assert(rval.size() == lval.size());