Rework parse rules to handle more net types.
This makes the rules for types to be more in line with IEEE1800.
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95
parse.y
95
parse.y
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@ -2,6 +2,7 @@
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%{
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/*
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* Copyright (c) 1998-2012 Stephen Williams (steve@icarus.com)
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* Copyright CERN 2012 / Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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@ -566,7 +567,7 @@ static void current_function_set_statement(const YYLTYPE&loc, vector<Statement*>
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%type <nettype> net_type var_type net_type_opt
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%type <gatetype> gatetype switchtype
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%type <porttype> port_direction port_direction_opt
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%type <vartype> primitive_type primitive_type_opt bit_logic
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%type <vartype> bit_logic
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%type <vartype> integer_vector_type
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%type <parmvalue> parameter_value_opt
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@ -3891,22 +3892,17 @@ module_item
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/* Modules can contain further sub-module definitions. */
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: module
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/* This rule detects net declarations that possibly include a
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primitive type, an optional vector range and signed flag. This
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also includes an optional delay set. The values are then applied
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to a list of names. If the primitive type is not specified, then
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resort to the default type LOGIC. */
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| attribute_list_opt net_type data_type_or_implicit delay3_opt net_variable_list ';'
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| attribute_list_opt net_type
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primitive_type_opt unsigned_signed_opt range_opt
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delay3_opt
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net_variable_list ';'
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{ vector_type_t*tmp = new vector_type_t($3, $4, $5);
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pform_set_data_type(@2, tmp, $7, $2, $1);
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if ($6 != 0) {
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yyerror(@6, "sorry: net delays not supported.");
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delete $6;
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{ data_type_t*data_type = $3;
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if (data_type == 0) {
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data_type = new vector_type_t(IVL_VT_LOGIC, false, 0);
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FILE_NAME(data_type, @2);
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}
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pform_set_data_type(@2, data_type, $5, $2, $1);
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if ($4 != 0) {
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yyerror(@2, "sorry: net delays not supported.");
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delete $4;
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}
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delete $1;
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}
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@ -3931,50 +3927,30 @@ module_item
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net_decl_assigns, which are <name> = <expr> assignment
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declarations. */
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| attribute_list_opt net_type
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primitive_type_opt unsigned_signed_opt range_opt
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delay3_opt net_decl_assigns ';'
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{ ivl_variable_type_t dtype = $3;
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if (dtype == IVL_VT_NO_TYPE)
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dtype = IVL_VT_LOGIC;
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vector_type_t*data_type = new vector_type_t(dtype, $4, $5);
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pform_makewire(@2, $6, str_strength, $7, $2, data_type);
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if ($1) {
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yyerror(@2, "sorry: Attributes not supported "
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"on net declaration assignments.");
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delete $1;
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}
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}
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/* Allow struct nets. */
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| attribute_list_opt net_type struct_data_type net_variable_list ';'
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{ pform_set_data_type(@2, $3, $4, $2, $1);
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delete $1;
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| attribute_list_opt net_type data_type_or_implicit delay3_opt net_decl_assigns ';'
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{ data_type_t*data_type = $3;
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if (data_type == 0) {
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data_type = new vector_type_t(IVL_VT_LOGIC, false, 0);
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FILE_NAME(data_type, @2);
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}
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pform_makewire(@2, $4, str_strength, $5, $2, data_type);
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if ($1) {
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yyerror(@2, "sorry: Attributes not supported "
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"on net declaration assignments.");
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delete $1;
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}
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}
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| attribute_list_opt net_type struct_data_type error ';'
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{ yyerror(@5, "error: Errors in net variable list.");
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}
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| attribute_list_opt net_type TYPE_IDENTIFIER net_variable_list ';'
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{ yyerror(@2, "sorry: Nets of named types not supported."); }
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/* This form doesn't have the range, but does have strengths. This
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gives strength to the assignment drivers. */
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| attribute_list_opt net_type
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primitive_type_opt unsigned_signed_opt
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drive_strength net_decl_assigns ';'
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{ ivl_variable_type_t dtype = $3;
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if (dtype == IVL_VT_NO_TYPE)
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dtype = IVL_VT_LOGIC;
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vector_type_t*data_type = new vector_type_t(dtype, $4, 0);
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pform_makewire(@2, 0, $5, $6, $2, data_type);
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| attribute_list_opt net_type data_type_or_implicit drive_strength net_decl_assigns ';'
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{ data_type_t*data_type = $3;
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if (data_type == 0) {
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data_type = new vector_type_t(IVL_VT_LOGIC, false, 0);
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FILE_NAME(data_type, @2);
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}
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pform_makewire(@2, 0, $4, $5, $2, data_type);
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if ($1) {
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yyerror(@2, "sorry: Attributes not supported "
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"on net declaration assignments.");
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@ -4369,20 +4345,11 @@ net_decl_assigns
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}
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;
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primitive_type
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: K_logic { $$ = IVL_VT_LOGIC; }
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| K_bool { $$ = IVL_VT_BOOL; /* Icarus Verilog xtypes */}
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| K_bit { $$ = IVL_VT_BOOL; /* IEEE1800 / IEEE1364-2009 */}
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| K_real { $$ = IVL_VT_REAL; }
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;
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bit_logic
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: K_logic { $$ = IVL_VT_LOGIC; }
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| K_bit { $$ = IVL_VT_BOOL; /* IEEE1800 / IEEE1364-2009 */}
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;
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primitive_type_opt : primitive_type { $$ = $1; } | { $$ = IVL_VT_NO_TYPE; } ;
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net_type
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: K_wire { $$ = NetNet::WIRE; }
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| K_tri { $$ = NetNet::TRI; }
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6
pform.cc
6
pform.cc
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@ -2880,6 +2880,11 @@ static void pform_set_enum(const struct vlltype&li, enum_type_t*enum_type,
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*/
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void pform_set_data_type(const struct vlltype&li, data_type_t*data_type, list<perm_string>*names, NetNet::Type net_type, list<named_pexpr_t>*attr)
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{
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if (data_type == 0) {
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VLerror(li, "internal error: data_type==0.");
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assert(0);
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}
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if (atom2_type_t*atom2_type = dynamic_cast<atom2_type_t*> (data_type)) {
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pform_set_integer_2atom(atom2_type->type_code, atom2_type->signed_flag, names, net_type, attr);
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return;
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@ -2922,6 +2927,7 @@ void pform_set_data_type(const struct vlltype&li, data_type_t*data_type, list<pe
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return;
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}
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VLerror(li, "internal error: Unexpected data_type.");
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assert(0);
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}
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