Generate VHDL array type declarations of Verilog arrays
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@ -270,14 +270,33 @@ static void declare_signals(vhdl_entity *ent, ivl_scope_t scope)
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ivl_signal_t sig = ivl_scope_sig(scope, i);
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remember_signal(sig, ent->get_arch()->get_scope());
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if (ivl_signal_dimensions(sig) > 0)
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error("Arrays not implemented yet");
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vhdl_type *sig_type =
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vhdl_type::type_for(ivl_signal_width(sig), ivl_signal_signed(sig) != 0);
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string name(make_safe_name(sig));
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rename_signal(sig, name);
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vhdl_type *sig_type;
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unsigned dimensions = ivl_signal_dimensions(sig);
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if (dimensions > 0) {
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// Arrays are implemented by generating a separate type
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// declaration for each array, and then declaring a
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// signal of that type
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if (dimensions > 1) {
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error("> 1 dimension arrays not implemented yet");
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return;
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}
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string type_name = name + "_Type";
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vhdl_type *base_type =
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vhdl_type::type_for(ivl_signal_width(sig), ivl_signal_signed(sig) != 0);
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vhdl_type *array_type = vhdl_type::array_of(base_type, type_name, 1, 0);
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vhdl_decl *array_decl = new vhdl_type_decl(type_name.c_str(), array_type);
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ent->get_arch()->get_scope()->add_decl(array_decl);
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sig_type = new vhdl_type(*array_type);
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}
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else
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sig_type =
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vhdl_type::type_for(ivl_signal_width(sig), ivl_signal_signed(sig) != 0);
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ivl_signal_port_t mode = ivl_signal_port(sig);
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switch (mode) {
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@ -380,11 +380,10 @@ void vhdl_signal_decl::emit(std::ostream &of, int level) const
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emit_comment(of, level, true);
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}
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void vhdl_type_decl::emit(std::ofstream &of, int level) const
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void vhdl_type_decl::emit(std::ostream &of, int level) const
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{
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of << "type " << name_ << " is ";
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type_->emit(of, level);
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of << ";";
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of << type_->get_type_decl_string() << ";";
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emit_comment(of, level, true);
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}
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@ -466,7 +466,7 @@ class vhdl_type_decl : public vhdl_decl {
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public:
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vhdl_type_decl(const char *name, vhdl_type *base)
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: vhdl_decl(name, base) {}
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void emit(std::ofstream &of, int level) const;
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void emit(std::ostream &of, int level) const;
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};
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@ -22,6 +22,7 @@
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#include <cassert>
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#include <sstream>
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#include <iostream>
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vhdl_type *vhdl_type::std_logic()
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@ -117,16 +118,27 @@ std::string vhdl_type::get_decl_string() const
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ss << " downto " << lsb_ << ")";
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return ss.str();
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}
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default:
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return get_string();
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}
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}
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/*
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* Like get_decl_string but completely expands array declarations.
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*/
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std::string vhdl_type::get_type_decl_string() const
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{
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switch (name_) {
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case VHDL_TYPE_ARRAY:
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{
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std::ostringstream ss;
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ss << "array (" << msb_ << " downto "
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<< lsb_ << ") of "
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<< base_->get_decl_string();
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return ss.str();
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return ss.str();
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}
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default:
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return get_string();
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return get_decl_string();
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}
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}
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@ -135,6 +147,22 @@ void vhdl_type::emit(std::ostream &of, int level) const
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of << get_decl_string();
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}
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vhdl_type::vhdl_type(const vhdl_type &other)
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: name_(other.name_), msb_(other.msb_), lsb_(other.lsb_),
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array_name_(other.array_name_)
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{
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if (other.base_ != NULL)
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base_ = new vhdl_type(*other.base_);
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else
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base_ = NULL;
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}
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vhdl_type::~vhdl_type()
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{
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if (base_ != NULL)
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delete base_;
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}
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vhdl_type *vhdl_type::std_logic_vector(int msb, int lsb)
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{
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return new vhdl_type(VHDL_TYPE_STD_LOGIC_VECTOR, msb, lsb);
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@ -53,13 +53,17 @@ public:
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int msb, int lsb)
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: name_(VHDL_TYPE_ARRAY), msb_(msb), lsb_(lsb), base_(base),
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array_name_(array_name) {}
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virtual ~vhdl_type() {}
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// Copy constructor
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vhdl_type(const vhdl_type &other);
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virtual ~vhdl_type();
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void emit(std::ostream &of, int level) const;
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vhdl_type_name_t get_name() const { return name_; }
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std::string get_string() const;
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std::string get_decl_string() const;
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std::string get_type_decl_string() const;
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vhdl_type *get_base() const;
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int get_width() const { return msb_ - lsb_ + 1; }
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int get_msb() const { return msb_; }
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