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Remove svector template from port handling.

This commit is contained in:
Stephen Williams 2013-02-24 18:06:12 -08:00
parent dd5fb47c6c
commit 25b48fa790
8 changed files with 109 additions and 81 deletions
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6
PFunction.cc
View File

@ -18,8 +18,8 @@
*/
# include "config.h"
#include "PTask.h"
# include "PTask.h"
# include <cassert>
PFunction::PFunction(perm_string name, LexicalScope*parent, bool is_auto__)
: PScope(name, parent), ports_(0), statement_(0)
@ -32,7 +32,7 @@ PFunction::~PFunction()
{
}
void PFunction::set_ports(svector<PWire *>*p)
void PFunction::set_ports(vector<PWire *>*p)
{
assert(ports_ == 0);
ports_ = p;

12
PTask.cc
View File

@ -18,11 +18,11 @@
*/
# include "config.h"
# include "PTask.h"
# include <cassert>
PTask::PTask(perm_string name, LexicalScope*parent, bool is_auto__)
: PScope(name, parent), ports_(0), statement_(0)
: PScope(name, parent), this_type_(0), ports_(0), statement_(0)
{
is_auto_ = is_auto__;
}
@ -31,7 +31,13 @@ PTask::~PTask()
{
}
void PTask::set_ports(svector<PWire*>*p)
void PTask::set_this(class_type_t*type)
{
assert(this_type_ == 0);
this_type_ = type;
}
void PTask::set_ports(vector<PWire*>*p)
{
assert(ports_ == 0);
ports_ = p;

21
PTask.h
View File

@ -21,7 +21,6 @@
# include "LineInfo.h"
# include "PScope.h"
# include "svector.h"
# include "StringHeap.h"
# include <string>
# include <vector>
@ -60,7 +59,8 @@ class PTask : public PScope, public LineInfo {
explicit PTask(perm_string name, LexicalScope*parent, bool is_auto);
~PTask();
void set_ports(svector<PWire *>*p);
void set_this(class_type_t*use_type);
void set_ports(std::vector<PWire *>*p);
void set_statement(Statement *s);
// Tasks introduce scope, to need to be handled during the
@ -77,10 +77,15 @@ class PTask : public PScope, public LineInfo {
bool is_auto() const { return is_auto_; };
// If this task is a method of a class, this returns a pointer
// to the class type.
inline class_type_t* method_of() const { return this_type_; }
void dump(ostream&, unsigned) const;
private:
svector<PWire*>*ports_;
class_type_t*this_type_;
std::vector<PWire*>*ports_;
Statement*statement_;
bool is_auto_;
@ -102,7 +107,8 @@ class PFunction : public PScope, public LineInfo {
explicit PFunction(perm_string name, LexicalScope*parent, bool is_auto);
~PFunction();
void set_ports(svector<PWire *>*p);
void set_this(class_type_t*use_type);
void set_ports(std::vector<PWire *>*p);
void set_statement(Statement *s);
void set_return(PTaskFuncArg t);
@ -116,11 +122,16 @@ class PFunction : public PScope, public LineInfo {
bool is_auto() const { return is_auto_; };
// If this function is a method of a class, this returns a
// pointer to the class type.
inline class_type_t* method_of() const { return this_type_; }
void dump(ostream&, unsigned) const;
private:
class_type_t*this_type_;
PTaskFuncArg return_type_;
svector<PWire *> *ports_;
std::vector<PWire *> *ports_;
Statement *statement_;
bool is_auto_;
};

6
elab_sig.cc
View File

@ -634,10 +634,10 @@ void PFunction::elaborate_sig(Design*des, NetScope*scope) const
}
}
vector<NetNet*>ports (ports_? ports_->count() : 0);
vector<NetNet*>ports (ports_? ports_->size() : 0);
if (ports_)
for (unsigned idx = 0 ; idx < ports_->count() ; idx += 1) {
for (unsigned idx = 0 ; idx < ports_->size() ; idx += 1) {
/* Parse the port name into the task name and the reg
name. We know by design that the port name is given
@ -710,7 +710,7 @@ void PTask::elaborate_sig(Design*des, NetScope*scope) const
elaborate_sig_wires_(des, scope);
svector<NetNet*>ports (ports_? ports_->count() : 0);
svector<NetNet*>ports (ports_? ports_->size() : 0);
for (unsigned idx = 0 ; idx < ports.count() ; idx += 1) {
perm_string port_name = (*ports_)[idx]->basename();

100
parse.y
View File

@ -366,7 +366,7 @@ static void current_function_set_statement(const YYLTYPE&loc, vector<Statement*>
PBlock::BL_TYPE join_keyword;
PWire*wire;
svector<PWire*>*wires;
vector<PWire*>*wires;
PEventStatement*event_statement;
Statement*statement;
@ -1619,7 +1619,7 @@ task_declaration /* IEEE1800-2005: A.2.7 */
tf_port_declaration /* IEEE1800-2005: A.2.7 */
: port_direction K_reg_opt unsigned_signed_opt range_opt list_of_identifiers ';'
{ svector<PWire*>*tmp = pform_make_task_ports(@1, $1,
{ vector<PWire*>*tmp = pform_make_task_ports(@1, $1,
$2 ? IVL_VT_LOGIC :
IVL_VT_NO_TYPE,
$3, $4, $5);
@ -1631,7 +1631,7 @@ tf_port_declaration /* IEEE1800-2005: A.2.7 */
| port_direction K_integer list_of_identifiers ';'
{ list<pform_range_t>*range_stub = make_range_from_width(integer_width);
svector<PWire*>*tmp = pform_make_task_ports(@1, $1, IVL_VT_LOGIC, true,
vector<PWire*>*tmp = pform_make_task_ports(@1, $1, IVL_VT_LOGIC, true,
range_stub, $3, true);
$$ = tmp;
}
@ -1640,16 +1640,16 @@ tf_port_declaration /* IEEE1800-2005: A.2.7 */
| port_direction K_time list_of_identifiers ';'
{ list<pform_range_t>*range_stub = make_range_from_width(64);
svector<PWire*>*tmp = pform_make_task_ports(@1, $1, IVL_VT_LOGIC, false,
range_stub, $3);
vector<PWire*>*tmp = pform_make_task_ports(@1, $1, IVL_VT_LOGIC, false,
range_stub, $3);
$$ = tmp;
}
/* Ports can be real or realtime. */
| port_direction real_or_realtime list_of_identifiers ';'
{ svector<PWire*>*tmp = pform_make_task_ports(@1, $1, IVL_VT_REAL, false,
0, $3);
{ vector<PWire*>*tmp = pform_make_task_ports(@1, $1, IVL_VT_REAL, false,
0, $3);
$$ = tmp;
}
@ -1677,10 +1677,10 @@ tf_port_item /* IEEE1800-2005: A.2.7 */
port_declaration_context.sign_flag = true;
delete port_declaration_context.range;
port_declaration_context.range = copy_range(range_stub);
svector<PWire*>*tmp = pform_make_task_ports(@3, use_port_type,
IVL_VT_LOGIC, true,
range_stub,
list_from_identifier($3), true);
vector<PWire*>*tmp = pform_make_task_ports(@3, use_port_type,
IVL_VT_LOGIC, true,
range_stub,
list_from_identifier($3), true);
$$ = tmp;
if ($4) {
yyerror(@4, "sorry: Port variable dimensions not supported yet.");
@ -1703,9 +1703,9 @@ tf_port_item /* IEEE1800-2005: A.2.7 */
port_declaration_context.sign_flag = false;
delete port_declaration_context.range;
port_declaration_context.range = copy_range(range_stub);
svector<PWire*>*tmp = pform_make_task_ports(@3, use_port_type, IVL_VT_LOGIC,
false, range_stub,
list_from_identifier($3));
vector<PWire*>*tmp = pform_make_task_ports(@3, use_port_type, IVL_VT_LOGIC,
false, range_stub,
list_from_identifier($3));
$$ = tmp;
if ($4) {
yyerror(@4, "sorry: Port variable dimensions not supported yet.");
@ -1718,7 +1718,7 @@ tf_port_item /* IEEE1800-2005: A.2.7 */
}
| port_direction_opt data_type_or_implicit IDENTIFIER range_opt tf_port_item_expr_opt
{ svector<PWire*>*tmp;
{ vector<PWire*>*tmp;
NetNet::PortType use_port_type = $1==NetNet::PIMPLICIT? NetNet::PINPUT : $1;
list<perm_string>* ilist = list_from_identifier($3);
@ -1784,10 +1784,13 @@ tf_port_item_expr_opt
tf_port_list /* IEEE1800-2005: A.2.7 */
: tf_port_list ',' tf_port_item
{ svector<PWire*>*tmp;
{ vector<PWire*>*tmp;
if ($1 && $3) {
tmp = new svector<PWire*>(*$1, *$3);
delete $1;
size_t s1 = $1->size();
tmp = $1;
tmp->resize(tmp->size()+$3->size());
for (size_t idx = 0 ; idx < $3->size() ; idx += 1)
tmp->at(s1+idx) = $3->at(idx);
delete $3;
} else if ($1) {
tmp = $1;
@ -3274,8 +3277,11 @@ function_item_list
| function_item_list function_item
{ /* */
if ($1 && $2) {
svector<PWire*>*tmp = new svector<PWire*>(*$1, *$2);
delete $1;
vector<PWire*>*tmp = $1;
size_t s1 = tmp->size();
tmp->resize(s1 + $2->size());
for (size_t idx = 0 ; idx < $2->size() ; idx += 1)
tmp->at(s1+idx) = $2->at(idx);
delete $2;
$$ = tmp;
} else if ($1) {
@ -5804,20 +5810,23 @@ analog_statement
/* Task items are, other than the statement, task port items and
other block items. */
task_item
: block_item_decl { $$ = new svector<PWire*>(0); }
| tf_port_declaration { $$ = $1; }
;
: block_item_decl { $$ = new vector<PWire*>(0); }
| tf_port_declaration { $$ = $1; }
;
task_item_list
: task_item_list task_item
{ svector<PWire*>*tmp = new svector<PWire*>(*$1, *$2);
delete $1;
delete $2;
$$ = tmp;
}
| task_item
{ $$ = $1; }
;
: task_item_list task_item
{ vector<PWire*>*tmp = $1;
size_t s1 = tmp->size();
tmp->resize(s1 + $2->size());
for (size_t idx = 0 ; idx < $2->size() ; idx += 1)
tmp->at(s1 + idx) = $2->at(idx);
delete $2;
$$ = tmp;
}
| task_item
{ $$ = $1; }
;
task_item_list_opt
: task_item_list
@ -5975,7 +5984,7 @@ udp_port_decl
| K_output IDENTIFIER ';'
{ perm_string pname = lex_strings.make($2);
PWire*pp = new PWire(pname, NetNet::IMPLICIT, NetNet::POUTPUT, IVL_VT_LOGIC);
svector<PWire*>*tmp = new svector<PWire*>(1);
vector<PWire*>*tmp = new vector<PWire*>(1);
(*tmp)[0] = pp;
$$ = tmp;
delete[]$2;
@ -5983,7 +5992,7 @@ udp_port_decl
| K_reg IDENTIFIER ';'
{ perm_string pname = lex_strings.make($2);
PWire*pp = new PWire(pname, NetNet::REG, NetNet::PIMPLICIT, IVL_VT_LOGIC);
svector<PWire*>*tmp = new svector<PWire*>(1);
vector<PWire*>*tmp = new vector<PWire*>(1);
(*tmp)[0] = pp;
$$ = tmp;
delete[]$2;
@ -5991,7 +6000,7 @@ udp_port_decl
| K_reg K_output IDENTIFIER ';'
{ perm_string pname = lex_strings.make($3);
PWire*pp = new PWire(pname, NetNet::REG, NetNet::POUTPUT, IVL_VT_LOGIC);
svector<PWire*>*tmp = new svector<PWire*>(1);
vector<PWire*>*tmp = new vector<PWire*>(1);
(*tmp)[0] = pp;
$$ = tmp;
delete[]$3;
@ -5999,15 +6008,18 @@ udp_port_decl
;
udp_port_decls
: udp_port_decl
{ $$ = $1; }
| udp_port_decls udp_port_decl
{ svector<PWire*>*tmp = new svector<PWire*>(*$1, *$2);
delete $1;
delete $2;
$$ = tmp;
}
;
: udp_port_decl
{ $$ = $1; }
| udp_port_decls udp_port_decl
{ vector<PWire*>*tmp = $1;
size_t s1 = $1->size();
tmp->resize(s1+$2->size());
for (size_t idx = 0 ; idx < $2->size() ; idx += 1)
tmp->at(s1+idx) = $2->at(idx);
$$ = tmp;
delete $2;
}
;
udp_port_list
: IDENTIFIER

33
pform.cc
View File

@ -1338,19 +1338,21 @@ static void process_udp_table(PUdp*udp, list<string>*table,
}
void pform_make_udp(perm_string name, list<perm_string>*parms,
svector<PWire*>*decl, list<string>*table,
vector<PWire*>*decl, list<string>*table,
Statement*init_expr,
const char*file, unsigned lineno)
{
unsigned local_errors = 0;
assert(!parms->empty());
assert(decl);
/* Put the declarations into a map, so that I can check them
off with the parameters in the list. If the port is already
in the map, merge the port type. I will rebuild a list
of parameters for the PUdp object. */
map<perm_string,PWire*> defs;
for (unsigned idx = 0 ; idx < decl->count() ; idx += 1) {
for (unsigned idx = 0 ; idx < decl->size() ; idx += 1) {
perm_string port_name = (*decl)[idx]->basename();
@ -2301,17 +2303,17 @@ void pform_makewire(const vlltype&li,
* constraints as those of tasks, so this works fine. Functions have
* no output or inout ports.
*/
svector<PWire*>*pform_make_task_ports(const struct vlltype&loc,
NetNet::PortType pt,
ivl_variable_type_t vtype,
bool signed_flag,
list<pform_range_t>*range,
list<perm_string>*names,
bool isint)
vector<PWire*>*pform_make_task_ports(const struct vlltype&loc,
NetNet::PortType pt,
ivl_variable_type_t vtype,
bool signed_flag,
list<pform_range_t>*range,
list<perm_string>*names,
bool isint)
{
assert(pt != NetNet::PIMPLICIT && pt != NetNet::NOT_A_PORT);
assert(names);
svector<PWire*>*res = new svector<PWire*>(0);
vector<PWire*>*res = new vector<PWire*>(0);
for (list<perm_string>::iterator cur = names->begin()
; cur != names->end() ; ++ cur ) {
@ -2336,10 +2338,7 @@ svector<PWire*>*pform_make_task_ports(const struct vlltype&loc,
curw->set_range(*range, SR_PORT);
}
svector<PWire*>*tmp = new svector<PWire*>(*res, curw);
delete res;
res = tmp;
res->push_back(curw);
}
delete range;
@ -2347,7 +2346,7 @@ svector<PWire*>*pform_make_task_ports(const struct vlltype&loc,
return res;
}
svector<PWire*>*pform_make_task_ports(const struct vlltype&loc,
vector<PWire*>*pform_make_task_ports(const struct vlltype&loc,
NetNet::PortType pt,
data_type_t*vtype,
list<perm_string>*names)
@ -2992,9 +2991,9 @@ void pform_set_data_type(const struct vlltype&li, data_type_t*data_type, list<pe
assert(0);
}
svector<PWire*>* pform_make_udp_input_ports(list<perm_string>*names)
vector<PWire*>* pform_make_udp_input_ports(list<perm_string>*names)
{
svector<PWire*>*out = new svector<PWire*>(names->size());
vector<PWire*>*out = new vector<PWire*>(names->size());
unsigned idx = 0;
for (list<perm_string>::iterator cur = names->begin()

8
pform.h
View File

@ -188,7 +188,7 @@ extern void pform_class_property(const struct vlltype&loc,
extern void pform_end_class_declaration(void);
extern void pform_make_udp(perm_string name, list<perm_string>*parms,
svector<PWire*>*decl, list<string>*table,
std::vector<PWire*>*decl, list<string>*table,
Statement*init,
const char*file, unsigned lineno);
@ -385,7 +385,7 @@ extern void pform_module_specify_path(PSpecPath*obj);
extern PProcess* pform_make_behavior(ivl_process_type_t, Statement*,
list<named_pexpr_t>*attr);
extern svector<PWire*>* pform_make_udp_input_ports(list<perm_string>*);
extern std::vector<PWire*>* pform_make_udp_input_ports(list<perm_string>*);
extern void pform_make_events(list<perm_string>*names,
const char*file, unsigned lineno);
@ -419,7 +419,7 @@ extern void pform_make_pgassign_list(list<PExpr*>*alist,
/* Given a port type and a list of names, make a list of wires that
can be used as task port information. */
extern svector<PWire*>*pform_make_task_ports(const struct vlltype&loc,
extern std::vector<PWire*>*pform_make_task_ports(const struct vlltype&loc,
NetNet::PortType pt,
ivl_variable_type_t vtype,
bool signed_flag,
@ -427,7 +427,7 @@ extern svector<PWire*>*pform_make_task_ports(const struct vlltype&loc,
list<perm_string>*names,
bool isint = false);
extern svector<PWire*>*pform_make_task_ports(const struct vlltype&loc,
extern std::vector<PWire*>*pform_make_task_ports(const struct vlltype&loc,
NetNet::PortType pt,
data_type_t*vtype,
list<perm_string>*names);

4
pform_dump.cc
View File

@ -910,7 +910,7 @@ void PFunction::dump(ostream&out, unsigned ind) const
out << pscope_name() << ";" << endl;
if (ports_)
for (unsigned idx = 0 ; idx < ports_->count() ; idx += 1) {
for (unsigned idx = 0 ; idx < ports_->size() ; idx += 1) {
out << setw(ind) << "";
out << "input ";
out << (*ports_)[idx]->basename() << ";" << endl;
@ -948,7 +948,7 @@ void PTask::dump(ostream&out, unsigned ind) const
if (is_auto_) cout << "automatic ";
out << pscope_name() << ";" << endl;
if (ports_)
for (unsigned idx = 0 ; idx < ports_->count() ; idx += 1) {
for (unsigned idx = 0 ; idx < ports_->size() ; idx += 1) {
if ((*ports_)[idx] == 0) {
out << setw(ind) << "" << "ERROR PORT" << endl;
continue;