Refactor assignment code
This commit is contained in:
Nick Gasson
parent
99ef8ec4f1
commit
8589c0691b
122
tgt-vhdl/stmt.cc
122
tgt-vhdl/stmt.cc
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@ -102,24 +102,21 @@ static int draw_noop(vhdl_procedural *proc, stmt_container *container,
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return 0;
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}
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/*
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* Generate an assignment of VHDL expr rhs to signal sig. This, unlike
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* the procedure below, is a generic routine used for more than just
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* Verilog signal assignment (e.g. it is used to expand ternary
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* expressions).
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*/
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template <class T>
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static T *make_vhdl_assignment(vhdl_procedural *proc, stmt_container *container,
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ivl_signal_t sig, vhdl_expr *rhs, bool blocking,
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vhdl_expr *base = NULL, unsigned lval_width = 0)
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static vhdl_expr *translate_assign_rhs(ivl_signal_t sig, vhdl_scope *scope,
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ivl_expr_t e, vhdl_expr *base,
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int lval_width)
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{
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std::string signame(get_renamed_signal(sig));
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vhdl_decl *decl = proc->get_scope()->get_decl(signame);
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vhdl_decl *decl = scope->get_decl(signame);
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assert(decl);
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vhdl_expr *rhs = translate_expr(e);
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if (rhs == NULL)
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return rhs;
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if (base == NULL)
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rhs = rhs->cast(decl->get_type());
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return rhs->cast(decl->get_type());
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else {
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vhdl_type integer(VHDL_TYPE_INTEGER);
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base = base->cast(&integer);
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@ -131,15 +128,29 @@ static T *make_vhdl_assignment(vhdl_procedural *proc, stmt_container *container,
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if (lval_width == 1) {
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vhdl_type t(VHDL_TYPE_STD_LOGIC);
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rhs = rhs->cast(&t);
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return rhs->cast(&t);
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}
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else {
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vhdl_type t(tname, lval_width);
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rhs = rhs->cast(&t);
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return rhs->cast(&t);
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}
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}
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}
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/*
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* Generate an assignment of VHDL expr rhs to signal sig. This, unlike
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* the procedure below, is a generic routine used for more than just
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* Verilog signal assignment (e.g. it is used to expand ternary
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* expressions).
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*/
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template <class T>
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static T *make_vhdl_assignment(vhdl_procedural *proc, stmt_container *container,
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ivl_signal_t sig, vhdl_expr *rhs, bool blocking,
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vhdl_expr *base = NULL, unsigned lval_width = 0)
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{
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bool isvar = strip_var(signame) != signame;
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// bool isvar = strip_var(signame) != signame;
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// Where possible, move constant assignments into the
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// declaration as initializers. This optimisation is only
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@ -155,11 +166,11 @@ static T *make_vhdl_assignment(vhdl_procedural *proc, stmt_container *container,
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// `always' process may then use the uninitialized signal value.
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// The second test ensures that we only try to initialise
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// internal signals not ports
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if (proc->get_scope()->initializing()
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/*if (proc->get_scope()->initializing()
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&& ivl_signal_port(sig) == IVL_SIP_NONE
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&& !decl->has_initial() && rhs->constant()
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&& container == proc->get_container() // Top-level container
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&& !isvar) {
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&& !isvar) {*/
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// decl->set_initial(new vhdl_expr(*rhs));
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@ -183,7 +194,7 @@ static T *make_vhdl_assignment(vhdl_procedural *proc, stmt_container *container,
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return a;
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}
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else*/
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}
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// }
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/*if (blocking && proc->get_scope()->allow_signal_assignment()) {
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// Remember we need to write the variable back to the
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@ -194,16 +205,8 @@ static T *make_vhdl_assignment(vhdl_procedural *proc, stmt_container *container,
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signame = get_renamed_signal(sig);
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}*/
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vhdl_type *ltype =
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new vhdl_type(*proc->get_scope()->get_decl(signame)->get_type());
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vhdl_var_ref *lval_ref = new vhdl_var_ref(signame.c_str(), ltype);
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if (base)
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lval_ref->set_slice(base, lval_width-1);
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T *a = new T(lval_ref, rhs);
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container->add_stmt(a);
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return a;
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// return a;
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}
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/*
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@ -243,20 +246,60 @@ static T *make_assignment(vhdl_procedural *proc, stmt_container *container,
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return NULL;
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vhdl_if_stmt *vhdif = new vhdl_if_stmt(test);
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make_vhdl_assignment<T>(proc, vhdif->get_then_container(), sig,
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/*make_vhdl_assignment<T>(proc, vhdif->get_then_container(), sig,
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true_part, blocking, base, lval_width);
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make_vhdl_assignment<T>(proc, vhdif->get_else_container(), sig,
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false_part, blocking, base, lval_width);
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*/
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container->add_stmt(vhdif);
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return NULL;
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}
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else {
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vhdl_expr *rhs = translate_expr(rval);
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vhdl_expr *rhs =
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translate_assign_rhs(sig, proc->get_scope(), rval, base, lval_width);
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if (NULL == rhs)
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return NULL;
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std::string signame(get_renamed_signal(sig));
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vhdl_decl *decl = proc->get_scope()->get_decl(signame);
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// Where possible, move constant assignments into the
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// declaration as initializers. This optimisation is only
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// performed on assignments of constant values to prevent
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// ordering problems.
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return make_vhdl_assignment<T>(proc, container, sig, rhs, blocking, base, lval_width);
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// This also has another application: If this is an `inital'
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// process and we haven't yet generated a `wait' statement then
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// moving the assignment to the initialization preserves the
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// expected Verilog behaviour: VHDL does not distinguish
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// `initial' and `always' processes so an `always' process might
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// be activatated before an `initial' process at time 0. The
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// `always' process may then use the uninitialized signal value.
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// The second test ensures that we only try to initialise
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// internal signals not ports
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if (proc->get_scope()->initializing()
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&& ivl_signal_port(sig) == IVL_SIP_NONE
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&& !decl->has_initial() && rhs->constant()
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&& container == proc->get_container()) { // Top-level container
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vhdl_expr *rhs_copy =
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translate_assign_rhs(sig, proc->get_scope(), rval,
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base, lval_width);
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decl->set_initial(rhs_copy);
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return NULL;
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}
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else {
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vhdl_type *ltype = new vhdl_type(*decl->get_type());
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vhdl_var_ref *lval_ref = new vhdl_var_ref(signame.c_str(), ltype);
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if (base)
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lval_ref->set_slice(base, lval_width-1);
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T *a = new T(lval_ref, rhs);
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container->add_stmt(a);
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return a;
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}
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}
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}
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else {
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@ -278,8 +321,11 @@ static int draw_nbassign(vhdl_procedural *proc, stmt_container *container,
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vhdl_nbassign_stmt *a =
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make_assignment<vhdl_nbassign_stmt>(proc, container, stmt, false);
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if (after != NULL)
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a->set_after(after);
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if (a != NULL) {
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// Assignment wasn't moved to initialisation
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if (after != NULL)
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a->set_after(after);
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}
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return 0;
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}
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@ -293,9 +339,11 @@ static int draw_assign(vhdl_procedural *proc, stmt_container *container,
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vhdl_nbassign_stmt *a =
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make_assignment<vhdl_nbassign_stmt>(proc, container, stmt, false);
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// Assignment is a statement and not moved into the initialisation
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//if (after != NULL)
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// a->set_after(after);
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if (a != NULL) {
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// Assignment is a statement and not moved into the initialisation
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//if (after != NULL)
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// a->set_after(after);
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}
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container->add_stmt
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(new vhdl_wait_stmt(VHDL_WAIT_FOR, new vhdl_const_time(0)));
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