Show tranif delays in the diagnostic dumps.

design_dump.cc

@@ -703,7 +703,14 @@ void NetTran::dump_node(ostream&o, unsigned ind) const
 	      << " part=" << part_width()
 	      << " offset=" << part_offset();
       }
-      o << endl;
+      o << " delay=(";
+      if (rise_time())
+	    o << *rise_time() << "," << *fall_time() << ","
+	      << *decay_time();
+      else
+	    o << "0,0,0";
+
+      o << ")" << endl;
       dump_node_pins(o, ind+4);
       dump_obj_attr(o, ind+4);
 }

tgt-stub/priv.h

@@ -43,6 +43,12 @@ extern ivl_variable_type_t type_of_nexus(ivl_nexus_t nex);
 
 extern ivl_discipline_t discipline_of_nexus(ivl_nexus_t nex);
 
+/*
+ * Test that a given expression is a valid delay expression, and
+ * print an error message if not.
+ */
+extern void test_expr_is_delay(ivl_expr_t expr);
+
 /*
  * Show the details of the expression.
  */

tgt-stub/stub.c

@@ -1343,7 +1343,7 @@ static void show_signal(ivl_signal_t net)
 
 }
 
-static void test_expr_is_delay(ivl_expr_t expr)
+void test_expr_is_delay(ivl_expr_t expr)
 {
       switch (ivl_expr_type(expr)) {
 	  case IVL_EX_ULONG:

tgt-stub/switches.c

@@ -63,6 +63,20 @@ void show_switch(ivl_switch_t net)
 
       fprintf(out, " island=%p\n", ivl_switch_island(net));
 
+      fprintf(out, "    <Delays...>\n");
+      if (ivl_switch_delay(net,0)) {
+	    test_expr_is_delay(ivl_switch_delay(net,0));
+	    show_expression(ivl_switch_delay(net,0), 6);
+      }
+      if (ivl_switch_delay(net,1)) {
+	    test_expr_is_delay(ivl_switch_delay(net,1));
+	    show_expression(ivl_switch_delay(net,1), 6);
+      }
+      if (ivl_switch_delay(net,2)) {
+	    test_expr_is_delay(ivl_switch_delay(net,2));
+	    show_expression(ivl_switch_delay(net,2), 6);
+      }
+
       nexa = ivl_switch_a(net);
       nex_type_a = nexa? type_of_nexus(nexa) : IVL_VT_NO_TYPE;
       fprintf(out, "    A: %p <type=%s>\n", nexa, data_type_string(nex_type_a));