Initial code to generate function calls
Also catch a few null-pointer issues
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c01c2bd742
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@ -203,6 +203,31 @@ vhdl_expr *translate_select(ivl_expr_t e)
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return from->resize(ivl_expr_width(e));
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}
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vhdl_expr *translate_ufunc(ivl_expr_t e)
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{
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ivl_scope_t defscope = ivl_expr_def(e);
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ivl_scope_t parentscope = ivl_scope_parent(defscope);
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assert(ivl_scope_type(parentscope) == IVL_SCT_MODULE);
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// A function is always declared in a module, which should have
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// a corresponding entity by this point: so we can get type
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// information, etc. from the declaration
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vhdl_entity *parent_ent = find_entity(ivl_scope_tname(parentscope));
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assert(parent_ent);
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const char *funcname = ivl_scope_tname(defscope);
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vhdl_decl *fdecl =
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parent_ent->get_arch()->get_scope()->get_decl(funcname);
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assert(fdecl);
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vhdl_type *rettype = new vhdl_type(*fdecl->get_type());
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vhdl_fcall *fcall = new vhdl_fcall(funcname, rettype);
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return fcall;
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}
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/*
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* Generate a VHDL expression from a Verilog expression.
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*/
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@ -224,6 +249,8 @@ vhdl_expr *translate_expr(ivl_expr_t e)
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return translate_binary(e);
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case IVL_EX_SELECT:
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return translate_select(e);
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case IVL_EX_UFUNC:
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return translate_ufunc(e);
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default:
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error("No VHDL translation for expression at %s:%d (type = %d)",
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ivl_expr_file(e), ivl_expr_lineno(e), type);
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@ -305,6 +305,12 @@ vhdl_decl::~vhdl_decl()
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delete initial_;
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}
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const vhdl_type *vhdl_decl::get_type() const
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{
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assert(type_);
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return type_;
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}
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void vhdl_decl::set_initial(vhdl_expr *initial)
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{
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if (initial_ != NULL)
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@ -414,7 +414,7 @@ public:
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virtual ~vhdl_decl();
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const std::string &get_name() const { return name_; }
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const vhdl_type *get_type() const { return type_; }
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const vhdl_type *get_type() const;
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void set_initial(vhdl_expr *initial);
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bool has_initial() const { return initial_ != NULL; }
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protected:
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