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Handle std_logic_vector library output stream 

When writing arrays to the work library, handle the special
case that it is an array of std_logic and write a std_logic_vector
declaration instead. This makes for a more compact description.
This commit is contained in:
Stephen Williams 2011-07-23 10:44:36 -07:00
parent df8efed22b
commit 148600814d
1 changed files with 11 additions and 0 deletions
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11
vhdlpp/vtype_stream.cc
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@ -30,6 +30,17 @@ void VType::write_to_stream(ostream&fd) const
void VTypeArray::write_to_stream(ostream&fd) const
{
// Special case: std_logic_vector
if (etype_ == &primitive_STDLOGIC) {
fd << "std_logic_vector";
if (ranges_.size() > 0) {
assert(ranges_.size() < 2);
fd << " (" << ranges_[0].msb()
<< " downto " << ranges_[0].lsb() << ") ";
}
return;
}
fd << "array ";
if (ranges_.size() > 0) {
assert(ranges_.size() < 2);