Add test for br_gh1248

This commit is contained in:
Cary R 2026-02-19 23:45:19 -08:00
parent b46fbe0892
commit 8385b13356
5 changed files with 101 additions and 0 deletions

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@ -0,0 +1,10 @@
0.000: x xxx x
1.000: x xx0 0
1.070: x x00 0
1.130: 0 000 0
2.000: 0 001 1
2.050: 0 011 1
2.120: 1 111 1
3.000: 1 110 0
3.070: 1 100 0
3.130: 0 000 0

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(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "br_gh1248")
(DATE "Thu Feb 19 22:00:00 2026")
(VENDOR "Custom")
(PROGRAM "Custom")
(VERSION "1.0.0")
(DIVIDER /)
(VOLTAGE 1.200)
(PROCESS "1.000")
(TEMPERATURE 25.000)
(TIMESCALE 1ns)
(CELL
(CELLTYPE "top")
(INSTANCE dut)
(DELAY
(ABSOLUTE
(INTERCONNECT i1/Y i2/A (0.010))
)
)
)
(CELL
(CELLTYPE "buff")
(INSTANCE dut/i1)
(DELAY
(ABSOLUTE
(IOPATH A Y (0.050) (0.070))
)
)
)
(CELL
(CELLTYPE "buff")
(INSTANCE dut/i2)
(DELAY
(ABSOLUTE
(IOPATH A Y (0.060) (0.050))
)
)
)
)

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`timescale 1ns/1ps
module tb;
reg in;
wire out;
top dut(out, in);
initial begin
$monitor("%.3f: %b %b %b",$realtime,out,dut.int,in);
$sdf_annotate("ivltests/br_gh1248.sdf");
#1;
in = 1'b0;
#1;
in = 1'b1;
#1;
in = 1'b0;
#1;
end
endmodule
module top(output wire out, input wire in);
wire [2:0] int;
assign int[0] = in;
buff i1 (.Y(int[1]), .A(int[0]));
buff i2 (.Y(int[2]), .A(int[1]));
assign out = int[2];
endmodule
`celldefine
module buff(output wire Y, input wire A);
buf (Y, A);
specify
(A => Y) = 0;
endspecify
endmodule
`endcelldefine

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@ -63,6 +63,7 @@ br_gh1180b vvp_tests/br_gh1180b.json
br_gh1181 vvp_tests/br_gh1181.json
br_gh1184 vvp_tests/br_gh1184.json
br_gh1242 vvp_tests/br_gh1242.json
br_gh1248 vvp_tests/br_gh1248.json
br_gh1256a vvp_tests/br_gh1256a.json
br_gh1256b vvp_tests/br_gh1256b.json
br_gh1258a vvp_tests/br_gh1258a.json

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{
"type" : "normal",
"source" : "br_gh1248.v",
"iverilog-args" : [ "-Ttyp", "-ginterconnect", "-gspecify" ],
"gold" : "br_gh1248",
"vlog95" : {
"__comment" : "The buffer module output is not connected.",
"type" : "TE"
}
}