Fix GitHub issue #352 - typo in README.txt (%time -> $time).
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@ -436,7 +436,7 @@ more details.
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Standard Verilog does not allow width fields in the %t formats
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of display strings. For example, this is illegal:
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$display("Time is %0t", %time);
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$display("Time is %0t", $time);
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Standard Verilog instead relies on the $timeformat to
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completely specify the format.
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