luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Debug messages for PGAssign elaboration.

This commit is contained in:
steve 2005-01-30 01:42:05 +00:00
parent 609b6a7baa
commit c23a35a033
1 changed files with 11 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
elaborate.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: elaborate.cc,v 1.315 2005/01/22 18:16:00 steve Exp $"
#ident "$Id: elaborate.cc,v 1.316 2005/01/30 01:42:05 steve Exp $"
#endif
# include "config.h"
@ -94,8 +94,8 @@ void PGAssign::elaborate(Design*des, NetScope*scope) const
assert(lval->pin_count() == 1);
if (debug_elaborate) {
cerr << lval->get_line() << ": debug: PGassign elaborated l-value "
<< "width=" << lval->vector_width() << endl;
cerr << lval->get_line() << ": debug: PGassign: elaborated l-value"
<< " width=" << lval->vector_width() << endl;
}
/* Handle the special case that the rval is simply an
@ -218,6 +218,11 @@ void PGAssign::elaborate(Design*des, NetScope*scope) const
return;
}
if (debug_elaborate) {
cerr << get_line() << ": debug: PGAssign: elaborated r-value"
<< " width="<<rval->vector_width() << endl;
}
assert(lval && rval);
assert(rval->pin_count() == 1);
@ -2880,6 +2885,9 @@ Design* elaborate(list<perm_string>roots)
/*
* $Log: elaborate.cc,v $
* Revision 1.316 2005/01/30 01:42:05 steve
* Debug messages for PGAssign elaboration.
*
* Revision 1.315 2005/01/22 18:16:00 steve
* Remove obsolete NetSubnet class.
*