Convert std_logic to Boolean in loop tests

tgt-vhdl/cast.cc

@@ -168,6 +168,8 @@ vhdl_expr *vhdl_const_bit::cast(const vhdl_type *to)
 {
    if (to->get_name() == VHDL_TYPE_INTEGER)
       return new vhdl_const_int(bit_ == '1' ? 1 : 0);
+   else if (to->get_name() == VHDL_TYPE_BOOLEAN)
+      return new vhdl_const_bool(bit_ == '1');
    else
       return vhdl_expr::cast(to);
 }

tgt-vhdl/stmt.cc

@@ -551,6 +551,11 @@ int draw_while(vhdl_procedural *proc, stmt_container *container,
    if (NULL == test)
       return 1;
 
+   // The test must be a Boolean (and std_logic and (un)signed types
+   // must be explicitly cast unlike in Verilog)
+   vhdl_type boolean(VHDL_TYPE_BOOLEAN);
+   test = test->cast(&boolean);
+
    vhdl_while_stmt *loop = new vhdl_while_stmt(test);
    container->add_stmt(loop);
 

tgt-vhdl/vhdl_syntax.cc

@@ -567,6 +567,11 @@ void vhdl_const_int::emit(std::ostream &of, int level) const
    of << value_;
 }
 
+void vhdl_const_bool::emit(std::ostream &of, int level) const
+{
+   of << (value_ ? "True" : "False");
+}
+
 void vhdl_const_time::emit(std::ostream &of, int level) const
 {
    of << value_;

tgt-vhdl/vhdl_syntax.hh

@@ -180,6 +180,15 @@ private:
    int64_t value_;
 };
 
+class vhdl_const_bool : public vhdl_expr {
+public:
+   vhdl_const_bool(bool value)
+      : vhdl_expr(vhdl_type::boolean(), true), value_(value) {}
+   void emit(std::ostream &of, int level) const;
+private:
+   bool value_;
+};
+
 class vhdl_expr_list : public vhdl_element {
 public:
    ~vhdl_expr_list();