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Fix assertion failure on illegal SV cast. 

Bug reported on iverilog-devel on 2018-02027.
This commit is contained in:
Martin Whitaker 2019-09-07 14:35:19 +01:00
parent b43fcccc0f
commit 34bb98676a
2 changed files with 19 additions and 2 deletions
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6
elab_expr.cc
View File

@ -1107,12 +1107,14 @@ unsigned PECallFunction::test_width_sfunc_(Design*des, NetScope*scope,
bool rc = eval_as_long(value, nexpr);
ivl_assert(*this, rc && value>=0);
// The argument type/width is self-determined and doesn't
// affect the result type/width.
// The argument width is self-determined and doesn't
// affect the result width.
width_mode_t arg_mode = SIZED;
parms_[0]->test_width(des, scope, arg_mode);
expr_type_ = pexpr->expr_type();
expr_width_ = value;
min_width_ = value;
signed_flag_= false;
return expr_width_;
}

15
netmisc.cc
View File

@ -925,6 +925,21 @@ static NetExpr* do_elab_and_eval(Design*des, NetScope*scope, PExpr*pe,
if (tmp == 0) return 0;
if ((cast_type != IVL_VT_NO_TYPE) && (cast_type != tmp->expr_type())) {
if (cast_type != pe->expr_type()) {
switch (pe->expr_type()) {
case IVL_VT_BOOL:
case IVL_VT_LOGIC:
case IVL_VT_REAL:
break;
default:
cerr << tmp->get_fileline() << ": error: "
"this expression cannot be implicitly "
"cast to the target type." << endl;
des->errors += 1;
delete tmp;
return 0;
}
}
switch (cast_type) {
case IVL_VT_REAL:
tmp = cast_to_real(tmp);