luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Check that logic gates are not given null ports. 

Logic gates do not handle null ports so check for this and
issue an error message when it happens.
This commit is contained in:
Cary R 2007-08-29 17:29:56 -07:00 committed by Stephen Williams
parent 4f6b47b345
commit 7bf4b64c0a
1 changed files with 12 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
elaborate.cc
View File

@ -379,6 +379,12 @@ void PGBuiltin::elaborate(Design*des, NetScope*scope) const
only. We do it early so that we can see if we can make a
wide gate instead of an array of gates. */
if (pin(0) == 0) {
cerr << get_line() << ": error: Logic gate port "
"expressions are not optional." << endl;
des->errors += 1;
return;
}
NetNet*lval_sig = pin(0)->elaborate_lnet(des, scope, true);
assert(lval_sig);
@ -536,6 +542,12 @@ void PGBuiltin::elaborate(Design*des, NetScope*scope) const
for (unsigned idx = 0 ; idx < pin_count() ; idx += 1) {
const PExpr*ex = pin(idx);
if (ex == 0) {
cerr << get_line() << ": error: Logic gate port "
"expressions are not optional." << endl;
des->errors += 1;
return;
}
NetNet*sig = (idx == 0)
? lval_sig
: ex->elaborate_net(des, scope, 0, 0, 0, 0);