luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

A time variable defaults to unsigned, but can be declared as signed

This commit is contained in:
Cary R 2020-07-07 20:32:00 -07:00
parent b8ae9a85fa
commit 018a649f59
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
parse.y
View File

@ -1202,9 +1202,9 @@ data_type /* IEEE1800-2005: A.2.2.1 */
tmp->integer_flag = true;
$$ = tmp;
}
| K_time
| K_time unsigned_signed_opt
{ list<pform_range_t>*pd = make_range_from_width(64);
vector_type_t*tmp = new vector_type_t(IVL_VT_LOGIC, false, pd);
vector_type_t*tmp = new vector_type_t(IVL_VT_LOGIC, $2, pd);
tmp->reg_flag = !gn_system_verilog();
$$ = tmp;
}