luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

vhdlpp: Emit VHDL 'integer' as SystemVerilog 'int'.

This commit is contained in:
Maciej Suminski 2014-10-09 10:29:14 +02:00
parent 4b60d2737e
commit 7f6100be2a
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
vhdlpp/library.cc
View File

@ -363,7 +363,7 @@ static void import_ieee_use(ActiveScope*res, perm_string package, perm_string na
const VTypePrimitive primitive_BOOLEAN(VTypePrimitive::BOOLEAN, true);
const VTypePrimitive primitive_BIT(VTypePrimitive::BIT, true);
const VTypePrimitive primitive_INTEGER(VTypePrimitive::INTEGER, true);
const VTypePrimitive primitive_INTEGER(VTypePrimitive::INTEGER);
const VTypePrimitive primitive_REAL(VTypePrimitive::REAL);
const VTypePrimitive primitive_STDLOGIC(VTypePrimitive::STDLOGIC, true);
const VTypePrimitive primitive_CHARACTER(VTypePrimitive::CHARACTER);

2
vhdlpp/vtype_emit.cc
View File

@ -146,7 +146,7 @@ int VTypePrimitive::emit_primitive_type(ostream&out) const
out << "logic";
break;
case INTEGER:
out << "bool[31:0]";
out << "int";
break;
case REAL:
out << "real";