Change architecture name to `FromVerilog'

tgt-vhdl/scope.cc

@@ -178,7 +178,7 @@ static vhdl_entity *create_entity_for(ivl_scope_t scope)
    // so we always create a pair and associate the architecture
    // with the entity for convenience (this also means that we
    // retain a 1-to-1 mapping of scope to VHDL element)
-   vhdl_arch *arch = new vhdl_arch(tname);
+   vhdl_arch *arch = new vhdl_arch(tname, "FromVerilog");
    vhdl_entity *ent = new vhdl_entity(tname, derived_from, arch);
 
    // Locate all the signals in this module and add them to

tgt-vhdl/vhdl_syntax.hh

@@ -405,7 +405,7 @@ private:
 class vhdl_arch : public vhdl_element {
    friend class vhdl_entity;  // Can set its parent
 public:
-   vhdl_arch(const char *entity, const char *name="Behavioural");
+   vhdl_arch(const char *entity, const char *name);
    virtual ~vhdl_arch();
 
    void emit(std::ofstream &of, int level=0) const;