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Tidy up whitespace in output

This commit is contained in:
Nick Gasson 2008-07-31 21:17:49 +01:00
parent 7b0f675785
commit d21277f1b9
1 changed files with 2 additions and 1 deletions
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3
tgt-vhdl/vhdl_syntax.cc
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@ -278,6 +278,7 @@ vhdl_component_decl *vhdl_component_decl::component_decl_for(vhdl_entity *ent)
void vhdl_component_decl::emit(std::ostream &of, int level) const
{
newline(of, level);
emit_comment(of, level);
of << "component " << name_ << " is";
@ -815,6 +816,7 @@ vhdl_function::vhdl_function(const char *name, vhdl_type *ret_type)
void vhdl_function::emit(std::ostream &of, int level) const
{
newline(of, level);
of << "function " << name_ << " (";
emit_children<vhdl_decl>(of, scope_.get_decls(), level, ";");
of << ") ";
@ -826,7 +828,6 @@ void vhdl_function::emit(std::ostream &of, int level) const
of << " return Verilog_Result;";
newline(of, level);
of << "end function;";
newline(of, level);
}
void vhdl_param_decl::emit(std::ostream &of, int level) const