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VHDL: make casez support 'x' and handle a full don't care case. 

The VHDL converter erroneously treated a casez and casex exactly
the same. In reality a casez compares a 'x' value (it is not a
don't care). It also adds support for a full don't care case by
just returning True for the condition.
This commit is contained in:
Cary R 2008-11-18 12:59:07 -08:00 committed by Stephen Williams
parent 35e0a98732
commit ec0e718151
1 changed files with 24 additions and 18 deletions
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42
tgt-vhdl/stmt.cc
View File

@ -608,30 +608,36 @@ int draw_casezx(vhdl_procedural *proc, stmt_container *container,
vhdl_binop_expr *all =
new vhdl_binop_expr(VHDL_BINOP_AND, vhdl_type::boolean());
bool just_dont_care = true;
for (unsigned i = 0; i < ivl_expr_width(net); i++) {
switch (bits[i]) {
case 'x':
if (ivl_statement_type(stmt) == IVL_ST_CASEZ) break;
case '?':
case 'z':
case 'x':
// Ignore it
break;
default:
{
// Generate a comparison for this bit position
vhdl_binop_expr *cmp =
new vhdl_binop_expr(VHDL_BINOP_EQ, vhdl_type::boolean());
vhdl_type *type = vhdl_type::nunsigned(ivl_expr_width(net));
vhdl_var_ref *lhs =
new vhdl_var_ref(test->get_name().c_str(), type);
lhs->set_slice(new vhdl_const_int(i));
cmp->add_expr(lhs);
cmp->add_expr(new vhdl_const_bit(bits[i]));
all->add_expr(cmp);
}
continue;
}
// Generate a comparison for this bit position
vhdl_binop_expr *cmp =
new vhdl_binop_expr(VHDL_BINOP_EQ, vhdl_type::boolean());
vhdl_type *type = vhdl_type::nunsigned(ivl_expr_width(net));
vhdl_var_ref *lhs =
new vhdl_var_ref(test->get_name().c_str(), type);
lhs->set_slice(new vhdl_const_int(i));
cmp->add_expr(lhs);
cmp->add_expr(new vhdl_const_bit(bits[i]));
all->add_expr(cmp);
just_dont_care = false;
}
// If there are no bits comparisons then just put a True
if (just_dont_care) {
all->add_expr(new vhdl_const_bool(true));
}
if (result)