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Generate code for signal references

This commit is contained in:
Nick Gasson 2008-06-07 11:24:09 +01:00
parent 5f90a3e48c
commit 305f448d05
2 changed files with 15 additions and 14 deletions
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12
tgt-vhdl/expr.cc
View File

@ -33,6 +33,16 @@ static vhdl_expr *translate_string(ivl_expr_t e)
return new vhdl_const_string(str);
}
/*
* A reference to a signal in an expression. It's assumed that the
* signal has already been defined elsewhere.
*/
static vhdl_expr *translate_signal(ivl_expr_t e)
{
ivl_signal_t sig = ivl_expr_signal(e);
return new vhdl_var_ref(ivl_signal_basename(sig));
}
/*
* Generate a VHDL expression from a Verilog expression.
*/
@ -43,6 +53,8 @@ vhdl_expr *translate_expr(ivl_expr_t e)
switch (type) {
case IVL_EX_STRING:
return translate_string(e);
case IVL_EX_SIGNAL:
return translate_signal(e);
default:
error("No VHDL translation for expression at %s:%d (type = %d)",
ivl_expr_file(e), ivl_expr_lineno(e), type);

17
tgt-vhdl/stmt.cc
View File

@ -178,23 +178,12 @@ static int draw_wait(vhdl_process *proc, ivl_statement_t stmt)
ivl_signal_t sig;
if ((sig = ivl_nexus_ptr_sig(nexus_ptr))) {
const char *signame = ivl_signal_basename(sig);
std::cout << "signal " << signame << std::endl;
if (!proc->get_parent()->have_declared(signame)) {
// First time this signal has been encountered
vhdl_scalar_type *std_logic =
new vhdl_scalar_type("std_logic");
vhdl_signal_decl *sig_decl =
new vhdl_signal_decl(signame, std_logic);
proc->get_parent()->add_decl(sig_decl);
}
std::cout << "signal " << signame << std::endl;
proc->add_sensitivity(signame);
}
else if ((log = ivl_nexus_ptr_log(nexus_ptr))) {
error("Nexus points to net logic");
return 1;
std::cout << "net logic " << ivl_logic_basename(log) << " ";
std::cout << "type = " << ivl_logic_type(log) << std::endl;
}
else {
error("Nexus points to unknown");