Merge branch 'master' into defparam-rework

elaborate.cc

@@ -1158,7 +1158,7 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
 
 		    /* Input to module. elaborate the expression to
 		       the desired width. If this in an instance
-		       array, then let the net determine it's own
+		       array, then let the net determine its own
 		       width. We use that, then, to decide how to hook
 		       it up.
 
@@ -2954,7 +2954,7 @@ NetForce* PForce::elaborate(Design*des, NetScope*scope) const
       dev = new NetForce(lval, rexp);
 
       if (debug_elaborate) {
-	    cerr << get_fileline() << ": debug: ELaborate force,"
+	    cerr << get_fileline() << ": debug: Elaborate force,"
 		 << " lval width=" << lval->lwidth()
 		 << " rval width=" << rexp->expr_width()
 		 << " rval=" << *rexp

ivlpp/lexor.lex

@@ -115,7 +115,7 @@ static void ifdef_enter(void)
     struct ifdef_stack_t*cur;
 
     cur = (struct ifdef_stack_t*) calloc(1, sizeof(struct ifdef_stack_t));
-    cur->path = strdup(istack->path);
+    if (istack->path) cur->path = strdup(istack->path);
     cur->lineno = istack->lineno;
     cur->next = ifdef_stack;
 
@@ -131,8 +131,10 @@ static void ifdef_leave(void)
     cur = ifdef_stack;
     ifdef_stack = cur->next;
 
-    if (strcmp(istack->path,cur->path) != 0)
-    {
+    /* If either path is from a non-file context e.g.(macro expansion)
+     * we assume that the non-file part is from this file. */
+    if (istack->path != NULL && cur->path != NULL &&
+        strcmp(istack->path,cur->path) != 0) {
         fprintf
         (
             stderr,

scripts/CREATE_VERSION.sh

@@ -8,6 +8,6 @@
 #    sh scripts/CREATE_VERSION.sh
 #
 
-echo "Building verion.h with git describe"
+echo "Building version.h with git describe"
 tmp=`git describe | sed -e 's;\(.*\);#define VERSION_TAG "\1";'`
 echo "$tmp" > version.h

t-dll.cc

@@ -1946,7 +1946,7 @@ void dll_target::lpm_mux(const NetMux*net)
 {
       ivl_lpm_t obj = new struct ivl_lpm_s;
       obj->type  = IVL_LPM_MUX;
-      obj->name  = net->name(); // The NetMux perallocates its name.
+      obj->name  = net->name(); // The NetMux permallocates its name.
       obj->scope = find_scope(des_, net->scope());
       assert(obj->scope);
 

tgt-fpga/iverilog-fpga.man

@@ -160,7 +160,7 @@ device pins are connected.
 .SH EXAMPLES
 
 .TB 8
-.I COMPILING WITH XILINX FOUNDATION/iSE
+.I COMPILING WITH XILINX FOUNDATION/ISE
 Compile a single-file design with command line tools like so:
 
 .nf

vvp/README.txt

@@ -802,7 +802,7 @@ syntax is:
 
 The <symbol> is the label for a variable array, and the <number> is
 the canonical word index as an unsigned integer. The second form
-retrives the index from thread space (<width> bits starting at <base>).
+retrieves the index from thread space (<width> bits starting at <base>).
 
 * The &PV<> argument
 

vvp/npmos.h

@@ -43,7 +43,7 @@
  *
  * This class also implements the NMOS device, which is the same as
  * the PMOS device, but the Control input inverted. The enable_invert
- * flag to the costructor activates this invertion.
+ * flag to the constructor activates this inversion.
  */
 
 class vvp_fun_pmos_ : public vvp_net_fun_t {

vvp/opcodes.txt

@@ -474,7 +474,7 @@ part. If any bit of the desired value is outside the vector, then that
 bit is set to X.
 
 The index register 1 is interpreted as a signed value. Even though the
-address is cannonical (from 0 to the width of the signal) the value in
+address is canonical (from 0 to the width of the signal) the value in
 index register 1 may be <0 or >=wid. The load instruction handles
 filling in the out-of-bounds bits with x.
 

vvp/schedule.cc

@@ -780,7 +780,7 @@ void schedule_simulate(void)
 			ctim->rwsync = 0;
 
 			  /* If out of rw events, then run the rosync
-			     events and delete this timestep. This also
+			     events and delete this time step. This also
 			     deletes threads as needed. */
 			if (ctim->active == 0) {
 			      run_rosync(ctim);

vvp/vpi_signal.cc

@@ -298,8 +298,7 @@ static void format_vpiIntVal(vvp_fun_signal_vec*sig, int base, unsigned wid,
 {
       vvp_vector4_t sub = sig->vec4_value().subvalue(base, wid);
       long val = 0;
-      bool flag = vector4_to_value(sub, val, signed_flag);
-      if (! flag) val = 0;
+      vector4_to_value(sub, val, signed_flag, false);
       vp->value.integer = val;
 }
 

vvp/vvp_island.cc

@@ -357,11 +357,11 @@ class vvp_island_tran : public vvp_island {
 void vvp_island_tran::run_island()
 {
 	// Test to see if any of the branches are enabled.
-      bool runable = false;
+      bool runnable = false;
       for (vvp_island_branch*cur = branches_ ; cur ; cur = cur->next_branch) {
-	    runable |= cur->run_test_enabled();
+	    runnable |= cur->run_test_enabled();
       }
-      if (runable == false)
+      if (runnable == false)
 	    return;
 
       for (vvp_island_branch*cur = branches_ ; cur ; cur = cur->next_branch)

vvp/vvp_net.cc

@@ -1133,10 +1133,12 @@ ostream& operator<< (ostream&out, const vvp_vector4_t&that)
       return out;
 }
 
-bool vector4_to_value(const vvp_vector4_t&vec, long&val, bool is_signed)
+bool vector4_to_value(const vvp_vector4_t&vec, long&val,
+		      bool is_signed, bool is_arithmetic)
 {
       long res = 0;
       long msk = 1;
+      bool rc_flag = true;
 
       for (unsigned idx = 0 ;  idx < vec.size() ;  idx += 1) {
 	    switch (vec.value(idx)) {
@@ -1146,7 +1148,10 @@ bool vector4_to_value(const vvp_vector4_t&vec, long&val, bool is_signed)
 		  res |= msk;
 		  break;
 		default:
-		  return false;
+		  if (is_arithmetic)
+			return false;
+		  else
+			rc_flag = false;
 	    }
 
 	    msk <<= 1L;
@@ -1158,7 +1163,7 @@ bool vector4_to_value(const vvp_vector4_t&vec, long&val, bool is_signed)
       }
 
       val = res;
-      return true;
+      return rc_flag;
 }
 
 bool vector4_to_value(const vvp_vector4_t&vec, unsigned long&val)

vvp/vvp_net.h

@@ -381,8 +381,15 @@ template <class T> extern T coerce_to_width(const T&that, unsigned width);
  * place (this follows the rules of Verilog conversions from vector4
  * to real and integers) and the return value becomes false to
  * indicate an error.
+ *
+ * The "is_arithmetic" flag true will cause a result to be entirely 0
+ * if any bits are X/Z. That is normally what you want if this value
+ * is in the midst of an arithmetic expression. If is_arithmetic=false
+ * then the X/Z bits will be replaced with 0 bits, and the return
+ * value will be "false", but the other bits will be transferred. This
+ * is what you want if you are doing "vpi_get_value", for example.
  */
-extern bool vector4_to_value(const vvp_vector4_t&a, long&val, bool is_signed);
+extern bool vector4_to_value(const vvp_vector4_t&a, long&val, bool is_signed, bool is_arithmetic =true);
 extern bool vector4_to_value(const vvp_vector4_t&a, unsigned long&val);
 extern bool vector4_to_value(const vvp_vector4_t&a, double&val, bool is_signed);