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Fix initialisation order bug with `if' statements 

If an assignment appears inside an if statement branch
it could be incorrectly used as the signal's initial
value.
This commit is contained in:
Nick Gasson 2008-07-16 12:11:00 +01:00
parent d343db34fd
commit 4504c2bceb
1 changed files with 18 additions and 14 deletions
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32
tgt-vhdl/stmt.cc
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@ -239,22 +239,26 @@ static T *make_assignment(vhdl_procedural *proc, stmt_container *container,
// internal signals not ports
if (proc->get_scope()->initializing()
&& ivl_signal_port(sig) == IVL_SIP_NONE
&& !decl->has_initial() && rhs->constant()
&& container == proc->get_container()) { // Top-level container
&& !decl->has_initial() && rhs->constant()) {
decl->set_initial(rhs);
return NULL;
}
else {
vhdl_var_ref *lval_ref =
make_assign_lhs(sig, proc->get_scope(), base, lval_width);
T *a = new T(lval_ref, rhs);
container->add_stmt(a);
return a;
// If this assignment is not in the top-level container
// it will not be made on all paths through the code
// This precludes any future extraction of an initialiser
if (container != proc->get_container())
decl->set_initial(NULL); // Default initial value
else {
decl->set_initial(rhs);
return NULL;
}
}
vhdl_var_ref *lval_ref =
make_assign_lhs(sig, proc->get_scope(), base, lval_width);
T *a = new T(lval_ref, rhs);
container->add_stmt(a);
return a;
}
}
else {