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At configure time, make sure prefix, exec_prefix and libdir are OK. 

Icarus Verilog internally is not white-space clean. We need to make
sure the configured paths that cause the most trouble are clean and
usable. It is still possible to mess things up downstream, but at least
this should help.
This commit is contained in:
Stephen Williams 2009-02-24 09:10:10 -08:00
parent 158e9fd2be
commit 2d6105a3f2
1 changed files with 25 additions and 0 deletions
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25
configure.in
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@ -176,6 +176,31 @@ AX_C_UNDERSCORES_TRAILING
## end of test for underscores
#######################
#######################
# Sanity check the configured results
#######################
AC_MSG_CHECKING(for sanity of prefix)
if test X`echo "$prefix" | wc -w` != X1
then
AC_MSG_ERROR(cannot configure white space in prefix: $prefix)
fi
AC_MSG_RESULT(ok)
AC_MSG_CHECKING(for sanity of exec_prefix)
if test X`echo "$exec_prefix" | wc -w` != X1
then
AC_MSG_ERROR(cannot configure white space in exec_prefix: $exec_prefix)
fi
AC_MSG_RESULT(ok)
AC_MSG_CHECKING(for sanity of libdir)
if test X`echo "$libdir" | wc -w` != X1
then
AC_MSG_ERROR(cannot configure white space in libdir: $libdir)
fi
AC_MSG_RESULT(ok)
# XXX disable tgt-fpga for the moment
AC_OUTPUT(Makefile ivlpp/Makefile vvp/Makefile vpi/Makefile driver/Makefile driver-vpi/Makefile cadpli/Makefile libveriuser/Makefile tgt-null/Makefile tgt-stub/Makefile tgt-vvp/Makefile tgt-vhdl/Makefile tgt-fpga/Makefile tgt-verilog/Makefile tgt-pal/Makefile)