Various improgements to expression ::synthesize methods
Since NetExpr::synthesize methods were rarely used, then had a lot of bugs. Now that continuous assign uses these methods, these bugs must be fixed. Binary and Unary minus properly pad/extens its arguments, Case compare generates correct code, Divide properly takes on signed flag, Signed right shift sign-extends its argument to prevent loss of sign bits and uses the NetSignExtend instead of simple padding, Use the correct target node for reduction NAND, Properly handle constant arguments of NetESelect Handle some exressions that were not handled before, include abs() and POW.
This commit is contained in:
Stephen Williams
parent
e8804500b0
commit
a8ad505af7
215
expr_synth.cc
215
expr_synth.cc
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@ -91,7 +91,7 @@ NetNet* NetExpr::synthesize(Design*des, NetScope*scope)
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*/
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NetNet* NetEBAdd::synthesize(Design*des, NetScope*scope)
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{
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assert((op()=='+') || (op()=='-'));
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ivl_assert(*this, (op()=='+') || (op()=='-'));
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NetNet *lsig=0, *rsig=0;
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bool real_args=false;
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@ -220,8 +220,14 @@ NetNet* NetEBComp::synthesize(Design*des, NetScope*scope)
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width = lsig->vector_width();
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if (rsig->vector_width() > width) width = rsig->vector_width();
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lsig = pad_to_width(des, lsig, width);
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rsig = pad_to_width(des, rsig, width);
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if (lsig->get_signed())
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lsig = pad_to_width_signed(des, lsig, width);
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else
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lsig = pad_to_width(des, lsig, width);
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if (rsig->get_signed())
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rsig = pad_to_width_signed(des, rsig, width);
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else
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rsig = pad_to_width(des, rsig, width);
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}
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NetNet*osig = new NetNet(scope, scope->local_symbol(),
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@ -231,10 +237,30 @@ NetNet* NetEBComp::synthesize(Design*des, NetScope*scope)
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osig->data_type(IVL_VT_LOGIC);
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bool signed_compare = lsig->get_signed() && rsig->get_signed();
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if (debug_elaborate) {
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cerr << get_fileline() << ": debug: Comparison (" << op_ << ")"
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<< " is " << (signed_compare? "signed" : "unsigned")
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<< endl;
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cerr << get_fileline() << ": : lsig is "
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<< (lsig->get_signed()? "signed" : "unsigned")
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<< " rsig is " << (rsig->get_signed()? "signed" : "unsigned")
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<< endl;
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}
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if (op_ == 'E' || op_ == 'N') {
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NetCaseCmp*gate = new NetCaseCmp(scope, scope->local_symbol(),
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width, op_=='E'?true:false);
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gate->set_line(*this);
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connect(gate->pin(0), osig->pin(0));
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connect(gate->pin(1), lsig->pin(0));
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connect(gate->pin(2), rsig->pin(0));
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des->add_node(gate);
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return osig;
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}
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/* Handle the special case of a single bit equality
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operation. Make an XNOR gate instead of a comparator. */
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if ((width == 1) && ((op_ == 'e') || (op_ == 'E')) && !real_args) {
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if ((width == 1) && (op_ == 'e') && !real_args) {
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NetLogic*gate = new NetLogic(scope, scope->local_symbol(),
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3, NetLogic::XNOR, 1);
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gate->set_line(*this);
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@ -248,7 +274,7 @@ NetNet* NetEBComp::synthesize(Design*des, NetScope*scope)
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/* Handle the special case of a single bit inequality
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operation. This is similar to single bit equality, but uses
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an XOR instead of an XNOR gate. */
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if ((width == 1) && ((op_ == 'n') || (op_ == 'N')) && !real_args) {
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if ((width == 1) && (op_ == 'n') && !real_args) {
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NetLogic*gate = new NetLogic(scope, scope->local_symbol(),
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3, NetLogic::XOR, 1);
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gate->set_line(*this);
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@ -404,6 +430,7 @@ NetNet* NetEBDiv::synthesize(Design*des, NetScope*scope)
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NetNet::IMPLICIT, width);
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osig->set_line(*this);
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osig->data_type(lsig->data_type());
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osig->set_signed(has_sign());
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osig->local_flag(true);
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switch (op()) {
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@ -414,6 +441,7 @@ NetNet* NetEBDiv::synthesize(Design*des, NetScope*scope)
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lsig->vector_width(),
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rsig->vector_width());
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div->set_line(*this);
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div->set_signed(has_sign());
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des->add_node(div);
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connect(div->pin_DataA(), lsig->pin(0));
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@ -552,8 +580,8 @@ NetNet* NetEBShift::synthesize(Design*des, NetScope*scope)
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return 0;
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}
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bool right_flag = op_ == 'r' || op_ == 'R';
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bool signed_flag = op_ == 'R';
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const bool right_flag = op_ == 'r' || op_ == 'R';
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const bool signed_flag = op_ == 'R';
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/* Detect the special case where the shift amount is
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constant. Evaluate the shift amount, and simply reconnect
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@ -562,7 +590,7 @@ NetNet* NetEBShift::synthesize(Design*des, NetScope*scope)
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verinum shift_v = rcon->value();
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long shift = shift_v.as_long();
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if (op() == 'r')
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if (right_flag)
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shift = 0-shift;
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if (shift == 0)
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@ -575,34 +603,13 @@ NetNet* NetEBShift::synthesize(Design*des, NetScope*scope)
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// ushift is the amount of pad created by the shift.
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unsigned long ushift = shift>=0? shift : -shift;
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if (ushift > osig->vector_width())
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ushift = osig->vector_width();
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ivl_assert(*this, ushift < osig->vector_width());
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// part_width is the bits of the vector that survive the shift.
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unsigned long part_width = osig->vector_width() - ushift;
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verinum znum (verinum::V0, ushift, true);
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NetConst*zcon = new NetConst(scope, scope->local_symbol(),
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znum);
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des->add_node(zcon);
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/* Detect the special case that the shift is the size of
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the whole expression. Simply connect the pad to the
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osig and escape. */
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if (ushift >= osig->vector_width()) {
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connect(zcon->pin(0), osig->pin(0));
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return osig;
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}
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NetNet*zsig = new NetNet(scope, scope->local_symbol(),
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NetNet::WIRE, znum.len());
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zsig->data_type(osig->data_type());
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zsig->local_flag(true);
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zsig->set_line(*this);
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connect(zcon->pin(0), zsig->pin(0));
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/* Create a part select to reduce the width of the lsig
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to the amount left by the shift. */
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// Create a part select to reduce the width of the lsig
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// to the amount left by the shift.
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NetPartSelect*psel = new NetPartSelect(lsig, shift<0? ushift : 0,
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part_width,
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NetPartSelect::VP);
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@ -615,6 +622,34 @@ NetNet* NetEBShift::synthesize(Design*des, NetScope*scope)
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psig->set_line(*this);
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connect(psig->pin(0), psel->pin(0));
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// Handle the special case of a signed right shift. In
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// this case, use the NetSignExtend device to pad the
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// result to the desired width.
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if (signed_flag && right_flag) {
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NetSignExtend*pad = new NetSignExtend(scope, scope->local_symbol(),
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osig->vector_width());
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des->add_node(pad);
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pad->set_line(*this);
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connect(pad->pin(1), psig->pin(0));
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connect(pad->pin(0), osig->pin(0));
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return osig;
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}
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// Other cases are handled by zero-extending on the
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// proper end.
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verinum znum (verinum::V0, ushift, true);
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NetConst*zcon = new NetConst(scope, scope->local_symbol(),
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znum);
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des->add_node(zcon);
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NetNet*zsig = new NetNet(scope, scope->local_symbol(),
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NetNet::WIRE, znum.len());
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zsig->data_type(osig->data_type());
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zsig->local_flag(true);
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zsig->set_line(*this);
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connect(zcon->pin(0), zsig->pin(0));
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NetConcat*ccat = new NetConcat(scope, scope->local_symbol(),
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osig->vector_width(), 2);
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ccat->set_line(*this);
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@ -674,7 +709,7 @@ NetNet* NetEConcat::synthesize(Design*des, NetScope*scope)
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if (flag == false)
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return 0;
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assert(tmp[0]);
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ivl_assert(*this, tmp[0]);
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/* Make a NetNet object to carry the output vector. */
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perm_string path = scope->local_symbol();
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@ -692,7 +727,9 @@ NetNet* NetEConcat::synthesize(Design*des, NetScope*scope)
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unsigned cur_pin = 1;
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for (unsigned rpt = 0; rpt < repeat(); rpt += 1) {
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for (unsigned idx = 0 ; idx < parms_.count() ; idx += 1) {
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connect(concat->pin(cur_pin), tmp[parms_.count()-idx-1]->pin(0));
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unsigned concat_item = parms_.count()-idx-1;
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ivl_assert(*this, tmp[concat_item]);
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connect(concat->pin(cur_pin), tmp[concat_item]->pin(0));
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cur_pin += 1;
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}
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}
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@ -787,9 +824,28 @@ NetNet* NetEUnary::synthesize(Design*des, NetScope*scope)
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return expr_->synthesize(des, scope);
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if (op_ == '-') {
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NetExpr*tmp = make_sub_expr(0, expr_);
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NetNet*sig = tmp->synthesize(des, scope);
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delete tmp;
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NetNet*sig = expr_->synthesize(des, scope);
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sig = sub_net_from(des, scope, 0, sig);
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return sig;
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}
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if (op_ == 'm') {
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NetNet*sub = expr_->synthesize(des, scope);
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if (expr_->has_sign() == false)
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return sub;
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NetNet*sig = new NetNet(scope, scope->local_symbol(),
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NetNet::WIRE, sub->vector_width());
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sig->set_line(*this);
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sig->local_flag(true);
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sig->data_type(sub->data_type());
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NetAbs*tmp = new NetAbs(scope, scope->local_symbol(), sub->vector_width());
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des->add_node(tmp);
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tmp->set_line(*this);
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connect(tmp->pin(1), sub->pin(0));
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connect(tmp->pin(0), sig->pin(0));
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return sig;
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}
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@ -835,7 +891,7 @@ NetNet* NetEUReduce::synthesize(Design*des, NetScope*scope)
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rtype = NetUReduce::XOR;
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break;
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case 'A':
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rtype = NetUReduce::XNOR;
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rtype = NetUReduce::NAND;
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break;
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case 'X':
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rtype = NetUReduce::XNOR;
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@ -857,6 +913,14 @@ NetNet* NetEUReduce::synthesize(Design*des, NetScope*scope)
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return osig;
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}
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/*
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* Turn a part/bit select expression into gates.
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* We know some things about the expression that elaboration enforces
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* for us:
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*
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* - Expression elaboration already converted the offset expression into
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* cannonical form, so we don't have to worry about that here.
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*/
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NetNet* NetESelect::synthesize(Design *des, NetScope*scope)
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{
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@ -866,6 +930,79 @@ NetNet* NetESelect::synthesize(Design *des, NetScope*scope)
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NetNet*off = 0;
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// Detect the special case that there is a base expression and
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// it is constant. In this case we can generate fixed part selects.
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if (NetEConst*base_const = dynamic_cast<NetEConst*>(base_)) {
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verinum base_tmp = base_const->value();
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ivl_assert(*this, base_tmp.is_defined());
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long base_val = base_tmp.as_long();
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unsigned select_width = expr_width();
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// Any below X bits?
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NetNet*below = 0;
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if (base_val < 0) {
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unsigned below_width = abs(base_val);
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base_val = 0;
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ivl_assert(*this, below_width < select_width);
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select_width -= below_width;
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below = make_const_x(des, scope, below_width);
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below->set_line(*this);
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}
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// Any above bits?.
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NetNet*above = 0;
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if (base_val+select_width > sub->vector_width()) {
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select_width = sub->vector_width() - base_val;
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unsigned above_width = expr_width() - select_width;
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above = make_const_x(des, scope, above_width);
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above->set_line(*this);
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}
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// Make the make part select.
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NetPartSelect*sel = new NetPartSelect(sub, base_val, select_width,
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NetPartSelect::VP);
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des->add_node(sel);
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NetNet*tmp = new NetNet(scope, scope->local_symbol(),
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NetNet::WIRE, select_width);
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tmp->data_type(sub->data_type());
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tmp->local_flag(true);
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tmp->set_line(*this);
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connect(sel->pin(0), tmp->pin(0));
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unsigned concat_count = 1;
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if (above)
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concat_count += 1;
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if (below)
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concat_count += 1;
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if (concat_count > 1) {
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NetConcat*cat = new NetConcat(scope, scope->local_symbol(),
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expr_width(), concat_count);
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cat->set_line(*this);
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des->add_node(cat);
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if (below) {
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connect(cat->pin(1), below->pin(0));
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connect(cat->pin(2), tmp->pin(0));
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} else {
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connect(cat->pin(1), tmp->pin(0));
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}
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if (above) {
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connect(cat->pin(concat_count), above->pin(0));
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}
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tmp = new NetNet(scope, scope->local_symbol(),
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NetNet::WIRE, expr_width());
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tmp->data_type(sub->data_type());
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tmp->local_flag(true);
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tmp->set_line(*this);
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connect(cat->pin(0), tmp->pin(0));
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}
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return tmp;
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}
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// This handles the case that the NetESelect exists to do an
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// actual part/bit select. Generate a NetPartSelect object to
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// do the work, and replace "sub" with the selected output.
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@ -977,7 +1114,7 @@ NetNet* NetETernary::synthesize(Design *des, NetScope*scope)
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perm_string path = csig->scope()->local_symbol();
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assert(csig->vector_width() == 1);
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ivl_assert(*this, csig->vector_width() == 1);
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unsigned width=expr_width();
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NetNet*osig = new NetNet(csig->scope(), path, NetNet::IMPLICIT, width);
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44
netmisc.cc
44
netmisc.cc
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@ -76,6 +76,36 @@ NetNet* add_to_net(Design*des, NetNet*sig, long val)
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#endif
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}
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NetNet* sub_net_from(Design*des, NetScope*scope, long val, NetNet*sig)
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{
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verinum zero ((uint64_t)0, sig->vector_width());
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NetConst*zero_obj = new NetConst(scope, scope->local_symbol(), zero);
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des->add_node(zero_obj);
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NetNet*zero_net = new NetNet(scope, scope->local_symbol(),
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NetNet::WIRE, sig->vector_width());
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zero_net->data_type(sig->data_type());
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zero_net->local_flag(true);
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connect(zero_net->pin(0), zero_obj->pin(0));
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NetAddSub*adder = new NetAddSub(scope, scope->local_symbol(), sig->vector_width());
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des->add_node(adder);
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adder->attribute(perm_string::literal("LPM_Direction"), verinum("SUB"));
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connect(zero_net->pin(0), adder->pin_DataA());
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connect(adder->pin_DataB(), sig->pin(0));
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NetNet*tmp = new NetNet(scope, scope->local_symbol(),
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NetNet::WIRE, sig->vector_width());
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tmp->data_type(sig->data_type());
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tmp->local_flag(true);
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connect(adder->pin_Result(), tmp->pin(0));
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return tmp;
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}
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NetNet* cast_to_int(Design*des, NetScope*scope, NetNet*src, unsigned wid)
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{
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if (src->data_type() != IVL_VT_REAL)
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@ -170,6 +200,20 @@ NetEConst* make_const_x(unsigned long wid)
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return resx;
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}
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NetNet* make_const_x(Design*des, NetScope*scope, unsigned long wid)
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{
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verinum xxx (verinum::Vx, wid);
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NetConst*res = new NetConst(scope, scope->local_symbol(), xxx);
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des->add_node(res);
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NetNet*sig = new NetNet(scope, scope->local_symbol(), NetNet::WIRE, wid);
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sig->local_flag(true);
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sig->data_type(IVL_VT_LOGIC);
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connect(sig->pin(0), res->pin(0));
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return sig;
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}
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NetExpr* condition_reduce(NetExpr*expr)
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{
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if (expr->expr_width() == 1)
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@ -91,6 +91,7 @@ extern NetNet*crop_to_width(Design*des, NetNet*n, unsigned w);
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* return a new NetNet value that is the output of an addition.
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*/
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extern NetNet*add_to_net(Design*des, NetNet*sig, long val);
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extern NetNet*sub_net_from(Design*des, NetScope*scope, long val, NetNet*sig);
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/*
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* These functions make various sorts of expressions, given operands
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@ -114,6 +115,11 @@ extern NetExpr*make_sub_expr(long val, NetExpr*expr);
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*/
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extern NetEConst*make_const_x(unsigned long wid);
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/*
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* Make A const net
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*/
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extern NetNet* make_const_x(Design*des, NetScope*scope, unsigned long wid);
|
||||
|
||||
/*
|
||||
* In some cases the lval is accessible as a pointer to the head of
|
||||
* a list of NetAssign_ objects. This function returns the width of
|
||||
|
|
|
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Reference in New Issue