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AND functor explicitly knows its width.

This commit is contained in:
steve 2005-06-26 21:08:38 +00:00
parent 1c6be44724
commit e3f300f4c2
2 changed files with 19 additions and 5 deletions
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16
vvp/logic.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: logic.cc,v 1.30 2005/06/26 18:06:29 steve Exp $"
#ident "$Id: logic.cc,v 1.31 2005/06/26 21:08:38 steve Exp $"
#endif
# include "logic.h"
@ -80,6 +80,12 @@ void table_functor_s::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&val)
vvp_send_vec4(ptr.ptr()->out, result);
}
vvp_fun_boolean_::vvp_fun_boolean_(unsigned wid)
{
for (unsigned idx = 0 ; idx < 4 ; idx += 1)
input_[idx] = vvp_vector4_t(wid);
}
vvp_fun_boolean_::~vvp_fun_boolean_()
{
}
@ -95,7 +101,8 @@ void vvp_fun_boolean_::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
schedule_generic(this, 0, false);
}
vvp_fun_and::vvp_fun_and()
vvp_fun_and::vvp_fun_and(unsigned wid)
: vvp_fun_boolean_(wid)
{
}
@ -260,7 +267,7 @@ void compile_functor(char*label, char*type, unsigned width,
obj = new table_functor_s(ft_OR);
} else if (strcmp(type, "AND") == 0) {
obj = new vvp_fun_and();
obj = new vvp_fun_and(width);
} else if (strcmp(type, "BUF") == 0) {
obj = new vvp_fun_buf();
@ -370,6 +377,9 @@ void compile_functor(char*label, char*type, unsigned width,
/*
* $Log: logic.cc,v $
* Revision 1.31 2005/06/26 21:08:38 steve
* AND functor explicitly knows its width.
*
* Revision 1.30 2005/06/26 18:06:29 steve
* AND gates propogate through scheduler, not directly.
*

8
vvp/logic.h
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: logic.h,v 1.20 2005/06/26 18:06:30 steve Exp $"
#ident "$Id: logic.h,v 1.21 2005/06/26 21:08:38 steve Exp $"
#endif
# include "vvp_net.h"
@ -52,6 +52,7 @@ class table_functor_s: public vvp_net_fun_t {
class vvp_fun_boolean_ : public vvp_net_fun_t, protected vvp_gen_event_s {
public:
explicit vvp_fun_boolean_(unsigned wid);
~vvp_fun_boolean_();
void recv_vec4(vvp_net_ptr_t p, const vvp_vector4_t&bit);
@ -63,7 +64,7 @@ class vvp_fun_boolean_ : public vvp_net_fun_t, protected vvp_gen_event_s {
class vvp_fun_and : public vvp_fun_boolean_ {
public:
explicit vvp_fun_and();
explicit vvp_fun_and(unsigned wid);
~vvp_fun_and();
private:
@ -142,6 +143,9 @@ extern const unsigned char ft_XOR[];
/*
* $Log: logic.h,v $
* Revision 1.21 2005/06/26 21:08:38 steve
* AND functor explicitly knows its width.
*
* Revision 1.20 2005/06/26 18:06:30 steve
* AND gates propogate through scheduler, not directly.
*