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VHDL process sensitivities go to the end of each iteration

This commit is contained in:
Stephen Williams 2012-03-31 10:42:35 -07:00
parent 78b0b49a4e
commit 5e7f61ea42
1 changed files with 16 additions and 10 deletions
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26
vhdlpp/architec_emit.cc
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@ -210,14 +210,27 @@ int IfGenerate::emit(ostream&out, Entity*ent, Architecture*arc)
return errors;
}
/*
* Emit a process statement using "always" syntax.
*
* Note that VHDL is different from Verilog, in that the sensitivity
* list goes at the END of the statement list, not at the
* beginning. In VHDL, all the statements are initially executed once
* before blocking in the first wait on the sensitivity list.
*/
int ProcessStatement::emit(ostream&out, Entity*ent, Architecture*arc)
{
int errors = 0;
out << "always";
out << "always begin" << endl;
for (list<SequentialStmt*>::iterator cur = statements_list_.begin()
; cur != statements_list_.end() ; ++cur) {
errors += (*cur)->emit(out, ent, arc);
}
if (! sensitivity_list_.empty()) {
out << " @(";
out << "@(";
const char*comma = 0;
for (list<Expression*>::iterator cur = sensitivity_list_.begin()
; cur != sensitivity_list_.end() ; ++cur) {
@ -226,14 +239,7 @@ int ProcessStatement::emit(ostream&out, Entity*ent, Architecture*arc)
errors += (*cur)->emit(out, ent, arc);
comma = ", ";
}
out << ")";
}
out << " begin" << endl;
for (list<SequentialStmt*>::iterator cur = statements_list_.begin()
; cur != statements_list_.end() ; ++cur) {
errors += (*cur)->emit(out, ent, arc);
out << ") /* sensitivity list for process */;" << endl;
}
out << "end" << endl;