Working on code generation for $display task
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@ -28,18 +28,32 @@
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* This is implemented using the functions in std.textio. Each
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* parameter is written to a line variable in the process and
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* then the line is written to the special variable `Output'
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* (which represents the console). Subsequent $displays will use
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* the same line variable.
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* (which represents the console). Subsequent $displays will
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* use the same line variable.
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*
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* It's possible, although quite unlikely, that there will be
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* name collision with an existing variable called
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* `Verilog_Display_Line' - do something about this? It's also
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* possible for there to be a name collision with the special
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* variable `Output'.
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* `Verilog_Display_Line' -- do something about this?
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* It's also possible for there to be a name collision with
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* the special variable `Output'.
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*/
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static int draw_stask_display(vhdl_process *proc, ivl_statement_t stmt)
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{
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require_package("std.textio");
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const char *display_line = "Verilog_Display_Line";
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if (!proc->have_declared_var(display_line)) {
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vhdl_type *line_type = new vhdl_scalar_type("Line");
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vhdl_var_decl *line_var =
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new vhdl_var_decl(display_line, line_type);
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line_var->set_comment("For generating $display output");
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proc->add_decl(line_var);
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}
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// TODO: Write the data into the line
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// TODO: Write_Line(Output, Verilog_Display_Line)
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return 0;
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}
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@ -67,16 +67,34 @@ void emit_children(std::ofstream &of,
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}
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}
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template <class T>
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void delete_children(std::list<T*> &children)
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{
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typename std::list<T*>::iterator it;
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for (it = children.begin(); it != children.end(); ++it)
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delete *it;
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children.clear();
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}
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void vhdl_element::set_comment(std::string comment)
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{
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comment_ = comment;
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}
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void vhdl_element::emit_comment(std::ofstream &of, int level) const
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/*
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* Draw the comment for any element. The comment is either on
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* a line before the element (end_of_line is false) or at the
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* end of the line containing the element (end_of_line is true).
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*/
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void vhdl_element::emit_comment(std::ofstream &of, int level,
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bool end_of_line) const
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{
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if (comment_.size() > 0) {
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if (end_of_line)
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of << " ";
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of << "-- " << comment_;
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newline(of, level);
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if (!end_of_line)
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newline(of, level);
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}
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}
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@ -112,17 +130,8 @@ vhdl_arch::vhdl_arch(const char *entity, const char *name)
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vhdl_arch::~vhdl_arch()
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{
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for (conc_stmt_list_t::iterator it = stmts_.begin();
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it != stmts_.end();
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++it)
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delete (*it);
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stmts_.clear();
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for (decl_list_t::iterator it = decls_.begin();
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it != decls_.end();
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++it)
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delete (*it);
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decls_.clear();
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delete_children<vhdl_conc_stmt>(stmts_);
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delete_children<vhdl_decl>(decls_);
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}
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void vhdl_arch::add_stmt(vhdl_conc_stmt *stmt)
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@ -172,10 +181,8 @@ vhdl_process::vhdl_process(const char *name)
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vhdl_process::~vhdl_process()
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{
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seq_stmt_list_t::iterator it;
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for (it = stmts_.begin(); it != stmts_.end(); ++it)
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delete (*it);
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stmts_.clear();
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delete_children<vhdl_seq_stmt>(stmts_);
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delete_children<vhdl_decl>(decls_);
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}
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void vhdl_process::add_stmt(vhdl_seq_stmt* stmt)
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@ -183,14 +190,28 @@ void vhdl_process::add_stmt(vhdl_seq_stmt* stmt)
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stmts_.push_back(stmt);
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}
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void vhdl_process::add_decl(vhdl_decl* decl)
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{
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decls_.push_back(decl);
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}
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bool vhdl_process::have_declared_var(const std::string &name) const
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{
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decl_list_t::const_iterator it;
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for (it = decls_.begin(); it != decls_.end(); ++it) {
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if ((*it)->get_name() == name)
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return true;
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}
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return false;
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}
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void vhdl_process::emit(std::ofstream &of, int level) const
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{
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emit_comment(of, level);
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if (name_.size() > 0)
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of << name_ << ": ";
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of << "process is"; // TODO: sensitivity
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newline(of, level);
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// ...declarations...
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emit_children<vhdl_decl>(of, decls_, level);
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of << "begin";
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emit_children<vhdl_seq_stmt>(of, stmts_, level);
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of << "end process;";
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@ -249,3 +270,16 @@ void vhdl_scalar_type::emit(std::ofstream &of, int level) const
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{
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of << name_;
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}
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vhdl_var_decl::~vhdl_var_decl()
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{
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delete type_;
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}
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void vhdl_var_decl::emit(std::ofstream &of, int level) const
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{
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of << "variable " << name_ << " : ";
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type_->emit(of, level);
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of << ";";
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emit_comment(of, level, true);
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}
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@ -38,7 +38,8 @@ public:
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void set_comment(std::string comment);
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protected:
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void emit_comment(std::ofstream &of, int level) const;
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void emit_comment(std::ofstream &of, int level,
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bool end_of_line=false) const;
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private:
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std::string comment_;
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};
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@ -55,7 +56,7 @@ public:
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* too much more complex, as Verilog's type system is much
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* simpler than VHDL's.
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*/
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class vhdl_scalar_type : public vhdl_element {
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class vhdl_scalar_type : public vhdl_type {
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public:
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vhdl_scalar_type(const char *name) : name_(name) {}
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@ -141,7 +142,13 @@ private:
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*/
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class vhdl_var_decl : public vhdl_decl {
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public:
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vhdl_var_decl(const char *name, vhdl_type *type)
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: vhdl_decl(name), type_(type) {}
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~vhdl_var_decl();
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void emit(std::ofstream &of, int level) const;
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private:
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vhdl_type *type_;
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};
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@ -172,8 +179,11 @@ public:
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void emit(std::ofstream &of, int level) const;
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void add_stmt(vhdl_seq_stmt *stmt);
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void add_decl(vhdl_decl *decl);
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bool have_declared_var(const std::string &name) const;
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private:
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seq_stmt_list_t stmts_;
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decl_list_t decls_;
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std::string name_;
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};
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