ivtest: Remove non-standard compliant test br_ml20150606

The br_ml20150606 regression test uses ANSI style port declarations, but
also re-declares the ports inside module as signals.

This is not valid (System)Verilog, even though the data type in the port
declaration is an implicit type. An ANSI-style port is always fully
defined. This defined section 23.2.2.2 ("ANSI style list of port
declarations") of the SystemVerilog LRM (1800-2017) and section 12.3.4
("List of ports declarations") of the Verilog LRM (1364-2005).

The test was originally added in response to a similarly non-compliant test
in the Yosys test suite, but that test has subsequently been updated to
conform to the standard[2].

Remove the non-compliant test in preparation for adding strict standard
compliance checking on ANSI port redeclarations.

[1] https://sourceforge.net/p/iverilog/mailman/message/34182256/
[2] https://github.com/YosysHQ/yosys/issues/1570

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

ivtest/ivltests/br_ml20150606.v

@@ -1,26 +0,0 @@
-module dut(input [3:0] DataI, output [3:0] DataO);
-
-wire [3:0] DataI;
-reg  [3:0] DataO;
-
-always @* DataO = DataI;
-
-endmodule
-
-module top();
-
-reg  [3:0] DataI;
-wire [3:0] DataO;
-
-dut dut(DataI, DataO);
-
-initial begin
-  DataI = 5;
-  #1;
-  if (DataO === 5)
-    $display("PASSED");
-  else
-    $display("FAILED");
-end
-
-endmodule

ivtest/regress-vlg.list

@@ -351,7 +351,6 @@ br_gh674		normal			ivltests
 br_gh732		normal			ivltests gold=br_gh732.gold
 br_ml20150315		normal			ivltests gold=br_ml_20150315.gold
 br_ml20150321		CE			ivltests
-br_ml20150606		normal			ivltests
 br_mw20171108		normal			ivltests
 br_ml20190806a		normal			ivltests
 br_ml20190806b		normal			ivltests