Merge pull request #594 from larsclausen/block-with-only-var-decl

Allow unnamed begin/end block with only variable declarations
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Stephen Williams 2022-01-23 10:41:48 -08:00 committed by GitHub
commit 32f01f87a6
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4 changed files with 33 additions and 6 deletions

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@ -0,0 +1,30 @@
// Check variable declarations in unnamed blocks
// All of these should pass in SystemVerilog and all but the last should fail in
// Verilog
module test;
initial begin
integer x;
end
initial begin
integer x;
integer y;
end
initial begin
integer x, y;
end
initial begin
integer x;
integer y;
x = y;
end
initial begin
$display("PASSED");
end
endmodule

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@ -82,6 +82,7 @@ pr3015421 CE ivltests gold=pr3015421-fsv.gold
resetall normal,-Wtimescale ivltests gold=resetall-fsv.gold
scope2b normal ivltests
sys_func_task_error RE ivltests gold=sys_func_task_error-fsv.gold
unnamed_block_var_decl normal ivltests
# We do not run synthesis when forcing SystemVerilog so these pass
br995 normal ivltests

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@ -1675,6 +1675,7 @@ undef_lval_select4b CE ivltests
undef_lval_select4c CE ivltests
undef_lval_select5 normal ivltests
undefined_shift normal ivltests
unnamed_block_var_decl CE ivltests
urand_r normal ivltests gold=urand_r.gold
urand_r2 normal ivltests gold=urand_r.gold
urand_r3 normal ivltests gold=urand_r.gold

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@ -6593,11 +6593,6 @@ statement_item /* This is roughly statement_item in the LRM */
name. These are handled by pushing the scope name, then matching
the declarations. The scope is popped at the end of the block. */
| K_begin K_end
{ PBlock*tmp = new PBlock(PBlock::BL_SEQ);
FILE_NAME(tmp, @1);
$$ = tmp;
}
/* In SystemVerilog an unnamed block can contain variable declarations. */
| K_begin
{ PBlock*tmp = pform_push_block_scope(@1, 0, PBlock::BL_SEQ);
@ -6618,7 +6613,7 @@ statement_item /* This is roughly statement_item in the LRM */
delete tmp;
}
}
statement_or_null_list K_end
statement_or_null_list_opt K_end
{ PBlock*tmp;
if ($3) {
pform_pop_scope();