Allow variables to implicitly convert to unresolved nets.
SystemVerilog allows variables to be either variables or unresolved nets, depending on how they are used. If they are assigned by procedural code, then they are variables. If they are assigned by a continuous assignment, they are unresolved nets. Note that they cannot be both, and when they are unresolved nets they can only be assigned once.
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568ee4436f
10
compiler.h
10
compiler.h
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@ -151,6 +151,16 @@ extern bool gn_io_range_error_flag;
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re-evaluated. */
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extern bool gn_strict_ca_eval_flag;
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/* If variables can be converted to uwires by a continuous assignment
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(assuming no procedural assign, then return true. This will be true
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for SystemVerilog */
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static inline bool gn_var_can_be_uwire(void)
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{
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if (generation_flag == GN_VER2009)
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return true;
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return false;
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}
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/* The bits of these GN_KEYWORDS_* constants define non-intersecting
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sets of keywords. The compiler enables groups of keywords by setting
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lexor_keyword_mask with the OR of the bits for the keywords to be
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16
elab_net.cc
16
elab_net.cc
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@ -414,6 +414,22 @@ NetNet* PEIdent::elaborate_lnet_common_(Design*des, NetScope*scope,
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assert(sig);
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/* If this is SystemVerilog and the variable is not yet
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assigned by anything, then convert it to an unresolved
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wire. */
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if (gn_var_can_be_uwire()
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&& (sig->type() == NetNet::REG)
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&& (sig->peek_eref() == 0) ) {
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sig->type(NetNet::UNRESOLVED_WIRE);
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}
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if (sig->type() == NetNet::UNRESOLVED_WIRE && sig->pin(0).is_linked()) {
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cerr << get_fileline() << ": error: Unresolved net " << sig->name()
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<< " cannot have multiple drivers." << endl;
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des->errors += 1;
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return 0;
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}
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/* Don't allow registers as assign l-values. */
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if (sig->type() == NetNet::REG) {
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cerr << get_fileline() << ": error: reg " << sig->name()
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@ -78,7 +78,7 @@ ostream& operator<< (ostream&o, NetNet::Type t)
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case NetNet::WIRE:
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o << "wire";
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break;
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case NetNet::UWIRE:
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case NetNet::UNRESOLVED_WIRE:
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o << "uwire";
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}
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return o;
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@ -553,7 +553,7 @@ class NetNet : public NetObj {
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public:
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enum Type { NONE, IMPLICIT, IMPLICIT_REG, INTEGER, WIRE, TRI, TRI1,
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SUPPLY0, SUPPLY1, WAND, TRIAND, TRI0, WOR, TRIOR, REG,
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UWIRE };
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UNRESOLVED_WIRE };
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enum PortType { NOT_A_PORT, PIMPLICIT, PINPUT, POUTPUT, PINOUT };
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4
parse.y
4
parse.y
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@ -2708,12 +2708,12 @@ net_type
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| K_supply1 { $$ = NetNet::SUPPLY1; }
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| K_wor { $$ = NetNet::WOR; }
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| K_trior { $$ = NetNet::TRIOR; }
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| K_wone { $$ = NetNet::UWIRE;
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| K_wone { $$ = NetNet::UNRESOLVED_WIRE;
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cerr << @1.text << ":" << @1.first_line << ": warning: "
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"'wone' is deprecated, please use 'uwire' "
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"instead." << endl;
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}
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| K_uwire { $$ = NetNet::UWIRE; }
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| K_uwire { $$ = NetNet::UNRESOLVED_WIRE; }
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;
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var_type
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