Add regression tests for `var` keyword
Check that the var keyword is supported in the following contexts * Module ports (both ANSI and non-ANSI) * Module variable declarations * Package variable declarations * Task and function ports * block variable declarations * for loop variable declarations Also check that it is an error to use the var keyword in a for loop without an explicit data type, as that is not allowed by the standard. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This commit is contained in:
Lars-Peter Clausen
parent
d753e6a5d0
commit
9ffe627b32
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@ -0,0 +1,50 @@
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// Check that the var keyword is supported for variable declarations in blocks
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`define check(val, exp) \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %b, got %b", `__LINE__, `"val`", val, exp); \
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failed = 1'b1; \
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end
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module test;
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bit failed = 1'b0;
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initial begin
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var x;
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var [7:0] y;
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var signed [8:0] z;
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var logic [9:0] w;
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x = 1'b1;
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y = 8'd10;
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z = -8'sd1;
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w = 8'd20;
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`check(x, 1'b1)
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`check(y, 10)
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`check(z, -1)
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`check(w, 20)
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// var should default to logic and allow x state
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x = 1'bx;
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y = 8'hxx;
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z = 8'hxx;
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w = 8'hxx;
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`check(x, 1'bx)
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`check(y, 8'hxx)
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`check(z, 8'hxx)
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`check(w, 8'hxx)
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`check($bits(x), 1)
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`check($bits(y), 8)
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`check($bits(z), 9)
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`check($bits(w), 10)
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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@ -0,0 +1,17 @@
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// Check that var keyword is supported in for loop variable declarations
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module test;
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initial begin
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int j;
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for (var int i = 0; i < 10; i++) begin
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j = i;
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end
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if (j == 9) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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end
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endmodule
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@ -0,0 +1,13 @@
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// Check that it is an error to not declare the data type in for loops, even
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// when using var
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module test;
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initial begin
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// The data type is not optional in a for loop, even when using var
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for (var [7:0] i = 0; i < 10; i++) begin
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end
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$display("FAILED");
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end
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endmodule
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@ -0,0 +1,41 @@
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// Check that the var keyword is supported for function ports
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`define check(val, exp) \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %b, got %b", `__LINE__, `"val`", val, exp); \
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return 1'b1; \
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end \
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return 1'b0;
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module test;
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function bit f1 (var int x);
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`check(x, 10)
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endfunction
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function bit f2 (input var int x);
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`check(x, 20)
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endfunction
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function bit f3 (var [7:0] x);
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`check(x, 30)
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endfunction
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function bit f4 (input var [7:0] x);
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`check(x, 40)
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endfunction
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initial begin
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bit failed;
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failed = f1(10);
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failed |= f2(20);
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failed |= f3(30);
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failed |= f4(40);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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// Check that the var keyword is supported for variable declarations in modules
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`define check(val, exp) \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %b, got %b", `__LINE__, `"val`", val, exp); \
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failed = 1'b1; \
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end
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module test;
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var x;
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var [7:0] y;
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var signed [8:0] z;
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var logic [9:0] w;
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bit failed = 1'b0;
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initial begin
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x = 1'b1;
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y = 8'd10;
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z = -8'sd1;
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w = 8'd20;
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`check(x, 1'b1)
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`check(y, 10)
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`check(z, -1)
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`check(w, 20)
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// var should default to logic and allow x state
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x = 1'bx;
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y = 8'hxx;
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z = 8'hxx;
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w = 8'hxx;
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`check(x, 1'bx)
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`check(y, 8'hxx)
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`check(z, 8'hxx)
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`check(w, 8'hxx)
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`check($bits(x), 1)
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`check($bits(y), 8)
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`check($bits(z), 9)
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`check($bits(w), 10)
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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@ -0,0 +1,11 @@
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// Check that using the var keyword for module ANSI inout ports results in an error
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module test #(
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inout var x
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);
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initial begin
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$display("FAILED");
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end
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endmodule
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@ -0,0 +1,10 @@
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// Check that using the var keyword for module non-ANSI inout ports results in an error
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module test;
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inout var x;
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initial begin
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$display("FAILED");
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end
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endmodule
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// Check that the var keyword is supported for module ANSI input ports
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bit failed = 1'b0;
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`define check(val, exp) \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %b, got %b", `__LINE__, `"val`", val, exp); \
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failed = 1'b1; \
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end
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module M #(
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parameter VAL_X = 0,
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parameter VAL_Y = 0,
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parameter VAL_Z = 0,
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parameter VAL_W = 0
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) (
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input var x,
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input var [7:0] y,
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input var signed [7:0] z,
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input var logic [7:0] w
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);
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initial begin
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`check(x, VAL_X)
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`check(y, VAL_Y)
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`check(z, VAL_Z)
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`check(w, VAL_W)
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end
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endmodule
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module test;
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M #(
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.VAL_X (1'b1),
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.VAL_Y (8'd10),
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.VAL_Z (-8'sd1),
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.VAL_W (8'd20)
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) i_m1 (
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.x (1'b1),
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.y (8'd10),
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.z (-8'sd1),
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.w (8'd20)
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);
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// When unconnected it should default to x, rather z
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M #(
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.VAL_X (1'bx),
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.VAL_Y (8'hx),
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.VAL_Z (8'hx),
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.VAL_W (8'hx)
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) i_m2 ();
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initial begin
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#1
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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// Check that the var keyword is supported for module non-ANSI input ports
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bit failed = 1'b0;
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`define check(val, exp) \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %b, got %b", `__LINE__, `"val`", val, exp); \
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failed = 1'b1; \
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end
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module M(x, y, z, w);
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parameter VAL_X = 0;
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parameter VAL_Y = 0;
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parameter VAL_Z = 0;
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parameter VAL_W = 0;
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input var x;
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input var [7:0] y;
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input var signed [7:0] z;
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input var logic [7:0] w;
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initial begin
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`check(x, VAL_X)
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`check(y, VAL_Y)
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`check(z, VAL_Z)
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`check(w, VAL_W)
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end
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endmodule
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module test;
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M #(
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.VAL_X (1'b1),
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.VAL_Y (8'd10),
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.VAL_Z (-8'sd1),
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.VAL_W (8'd20)
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) i_m1 (
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.x (1'b1),
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.y (8'd10),
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.z (-8'sd1),
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.w (8'd20)
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);
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// When unconnected it should default to x, rather z
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M #(
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.VAL_X (1'bx),
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.VAL_Y (8'hx),
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.VAL_Z (8'hx),
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.VAL_W (8'hx)
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) i_m2 ();
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initial begin
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#1
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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@ -0,0 +1,81 @@
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// Check that the var keyword is supported for module ANSI output ports
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bit failed = 1'b0;
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`define check(val, exp) \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %b, got %b", `__LINE__, `"val`", val, exp); \
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failed = 1'b1; \
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end
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module M #(
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parameter VAL_X = 0,
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parameter VAL_Y = 0,
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parameter VAL_Z = 0,
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parameter VAL_W = 0
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) (
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output var x,
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output var [7:0] y,
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output var signed [7:0] z,
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output var logic [7:0] w
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);
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assign x = VAL_X;
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assign y = VAL_Y;
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assign z = VAL_Z;
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assign w = VAL_W;
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endmodule
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module test;
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logic x1;
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logic x2;
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logic [7:0] y1;
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logic [7:0] y2;
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logic signed [7:0] z1;
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logic signed [7:0] z2;
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logic [7:0] w1;
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logic [7:0] w2;
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M #(
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.VAL_X (1'b1),
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.VAL_Y (10),
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.VAL_Z (-1),
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.VAL_W (20)
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) i_m1 (
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.x (x1),
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.y (y1),
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.z (z1),
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.w (w1)
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);
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// The type for var should default to logic, check that the value can be X
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M #(
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.VAL_X (1'bx),
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.VAL_Y (8'hxx),
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.VAL_Z (8'hxx),
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.VAL_W (8'hxx)
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) i_m2 (
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.x (x2),
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.y (y2),
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.z (z2),
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.w (w2)
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);
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initial begin
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`check(x1, 1'b1)
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`check(y1, 10)
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`check(z1, -1)
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`check(w1, 20)
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`check(x2, 1'bx)
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`check(y2, 8'hxx)
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`check(z2, 8'hxx)
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`check(w2, 8'hxx)
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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@ -0,0 +1,80 @@
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// Check that the var keyword is supported for module non-ANSI output ports
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bit failed = 1'b0;
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`define check(val, exp) \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %b, got %b", `__LINE__, `"val`", val, exp); \
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failed = 1'b1; \
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end
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module M(x, y, z, w);
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parameter VAL_X = 0;
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parameter VAL_Y = 0;
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parameter VAL_Z = 0;
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parameter VAL_W = 0;
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output var x;
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output var [7:0] y;
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output var signed [7:0] z;
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output var logic [7:0] w;
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assign x = VAL_X;
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assign y = VAL_Y;
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assign z = VAL_Z;
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assign w = VAL_W;
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endmodule
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module test;
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logic x1;
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logic x2;
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logic [7:0] y1;
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logic [7:0] y2;
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logic signed [7:0] z1;
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logic signed [7:0] z2;
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logic [7:0] w1;
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logic [7:0] w2;
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M #(
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.VAL_X (1'b1),
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.VAL_Y (10),
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.VAL_Z (-1),
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.VAL_W (20)
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) i_m1 (
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.x (x1),
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.y (y1),
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.z (z1),
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.w (w1)
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);
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// The type for var should default to logic, check that the value can be X
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M #(
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.VAL_X (1'bx),
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.VAL_Y (8'hxx),
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.VAL_Z (8'hxx),
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.VAL_W (8'hxx)
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) i_m2 (
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.x (x2),
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.y (y2),
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.z (z2),
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.w (w2)
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);
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initial begin
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`check(x1, 1'b1)
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`check(y1, 10)
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`check(z1, -1)
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`check(w1, 20)
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`check(x2, 1'bx)
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`check(y2, 8'hxx)
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`check(z2, 8'hxx)
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`check(w2, 8'hxx)
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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@ -0,0 +1,53 @@
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// Check that the var keyword is supported for variable declarations in packages
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`define check(val, exp) \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %b, got %b", `__LINE__, `"val`", val, exp); \
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failed = 1'b1; \
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end
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package P;
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var x;
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var [7:0] y;
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var signed [8:0] z;
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var logic [9:0] w;
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endpackage
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module test;
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import P::*;
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bit failed = 1'b0;
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initial begin
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x = 1'b1;
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y = 8'd10;
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z = -8'sd1;
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w = 8'd20;
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`check(x, 1'b1)
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`check(y, 10)
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`check(z, -1)
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`check(w, 20)
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// var should default to logic and allow x state
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x = 1'bx;
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y = 8'hxx;
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z = 8'hxx;
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w = 8'hxx;
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`check(x, 1'bx)
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`check(y, 8'hxx)
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`check(z, 8'hxx)
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`check(w, 8'hxx)
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`check($bits(x), 1)
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`check($bits(y), 8)
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`check($bits(z), 9)
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`check($bits(w), 10)
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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|
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@ -0,0 +1,48 @@
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// Check that the var keyword is supported for task ports
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bit failed = 1'b0;
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`define check(val, exp) \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %b, got %b", `__LINE__, `"val`", val, exp); \
|
||||
failed = 1'b1; \
|
||||
end
|
||||
|
||||
module test;
|
||||
|
||||
task t1 (var int x);
|
||||
`check(x, 10)
|
||||
endtask
|
||||
|
||||
task t2 (input var int x, output var int y);
|
||||
`check(x, 20)
|
||||
y = x;
|
||||
endtask
|
||||
|
||||
task t3 (var [7:0] x);
|
||||
`check(x, 30)
|
||||
endtask
|
||||
|
||||
task t4 (input var [7:0] x, output var [7:0] y);
|
||||
`check(x, 40)
|
||||
y = x;
|
||||
endtask
|
||||
|
||||
initial begin
|
||||
int o1;
|
||||
logic [7:0] o2;
|
||||
|
||||
t1(10);
|
||||
t2(20, o1);
|
||||
t3(30);
|
||||
t4(40, o2);
|
||||
|
||||
`check(o1, 20)
|
||||
`check(o2, 40)
|
||||
|
||||
if (!failed) begin
|
||||
$display("PASSED");
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -694,8 +694,21 @@ sv_uwire1 normal,-g2009 ivltests
|
|||
sv_uwire2 normal,-g2009 ivltests
|
||||
sv_uwire3 normal,-g2009 ivltests
|
||||
sv_uwire4 normal,-g2009 ivltests
|
||||
sv_var_block normal,-g2005-sv ivltests
|
||||
sv_var_for normal,-g2005-sv ivltests
|
||||
sv_var_for_fail CE,-g2005-sv ivltests
|
||||
sv_var_function normal,-g2005-sv ivltests
|
||||
sv_var_init1 normal,-g2009 ivltests
|
||||
sv_var_init2 normal,-g2009 ivltests
|
||||
sv_var_module normal,-g2005-sv ivltests
|
||||
sv_var_module_inout1 CE,-g2005-sv ivltests
|
||||
sv_var_module_inout2 CE,-g2005-sv ivltests
|
||||
sv_var_module_input1 normal,-g2005-sv ivltests
|
||||
sv_var_module_input2 normal,-g2005-sv ivltests
|
||||
sv_var_module_output1 normal,-g2005-sv ivltests
|
||||
sv_var_module_output2 normal,-g2005-sv ivltests
|
||||
sv_var_package normal,-g2005-sv ivltests
|
||||
sv_var_task normal,-g2005-sv ivltests
|
||||
sv_wildcard_import1 normal,-g2009 ivltests
|
||||
sv_wildcard_import2 normal,-g2009 ivltests
|
||||
sv_wildcard_import3 normal,-g2009 ivltests
|
||||
|
|
|
|||
|
|
@ -942,6 +942,17 @@ sv_port_default10 normal,-g2009,-pallowsigned=1 ivltests
|
|||
sv_port_default11 normal,-g2009,-pallowsigned=1 ivltests
|
||||
sv_root_func normal,-g2009,-pallowsigned=1 ivltests gold=sv_root_func.gold
|
||||
sv_root_task normal,-g2009,-pallowsigned=1 ivltests gold=sv_root_task.gold
|
||||
sv_var_block normal,-g2005-sv,-pallowsigned=1 ivltests
|
||||
sv_var_for normal,-g2005-sv,-pallowsigned=1 ivltests
|
||||
sv_var_function normal,-g2005-sv,-pallowsigned=1 ivltests
|
||||
sv_var_module normal,-g2005-sv,-pallowsigned=1 ivltests
|
||||
# Inputs can not be reg in Verilog 95, so the translated code will fail
|
||||
sv_var_module_input1 TE,-g2005-sv,-pallowsigned=1 ivltests
|
||||
sv_var_module_input2 TE,-g2005-sv,-pallowsigned=1 ivltests
|
||||
sv_var_module_output1 normal,-g2005-sv,-pallowsigned=1 ivltests
|
||||
sv_var_module_output2 normal,-g2005-sv,-pallowsigned=1 ivltests
|
||||
sv_var_package normal,-g2005-sv,-pallowsigned=1 ivltests
|
||||
sv_var_task normal,-g2005-sv,-pallowsigned=1 ivltests
|
||||
test_dispwided normal,-pallowsigned=1 ivltests gold=test_dispwided.gold
|
||||
test_inc_dec normal,-g2009,-pallowsigned=1 ivltests
|
||||
test_enumsystem normal,-g2009,-pallowsigned=1,ivltests/enumsystem.vhd ivltests
|
||||
|
|
|
|||
Loading…
Reference in New Issue