Part selects are done in the compiler, not here.
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: eval_expr.c,v 1.111 2004/12/11 02:31:28 steve Exp $"
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#ident "$Id: eval_expr.c,v 1.112 2005/01/24 05:08:02 steve Exp $"
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#endif
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# include "vvp_priv.h"
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@ -1457,16 +1457,12 @@ static struct vector_info draw_string_expr(ivl_expr_t exp, unsigned wid)
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static void draw_signal_dest(ivl_expr_t exp, struct vector_info res)
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{
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unsigned idx;
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unsigned lsi = ivl_expr_lsi(exp);
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unsigned swid = ivl_expr_width(exp);
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ivl_signal_t sig = ivl_expr_signal(exp);
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if (swid > res.wid)
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swid = res.wid;
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/* XXXX I forget how to do part selects here. */
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assert(lsi == 0);
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/* If this is a REG (a variable) then I can do a vector read. */
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fprintf(vvp_out, " %%load/v %u, V_%s, %u;\n",
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res.base, vvp_signal_label(sig), swid);
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@ -2129,6 +2125,9 @@ struct vector_info draw_eval_expr(ivl_expr_t exp, int stuff_ok_flag)
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/*
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* $Log: eval_expr.c,v $
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* Revision 1.112 2005/01/24 05:08:02 steve
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* Part selects are done in the compiler, not here.
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*
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* Revision 1.111 2004/12/11 02:31:28 steve
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* Rework of internals to carry vectors through nexus instead
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* of single bits. Make the ivl, tgt-vvp and vvp initial changes
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@ -16,7 +16,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: vector.c,v 1.4 2003/07/03 17:44:10 steve Exp $"
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#ident "$Id: vector.c,v 1.5 2005/01/24 05:08:02 steve Exp $"
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#endif
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# include "vvp_priv.h"
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@ -147,9 +147,6 @@ static int compare_exp(ivl_expr_t l, ivl_expr_t r)
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if (ivl_expr_signal(l) != ivl_expr_signal(r))
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return 0;
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if (ivl_expr_lsi(l) != ivl_expr_lsi(r))
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return 0;
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if (ivl_expr_width(l) != ivl_expr_width(r))
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return 0;
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@ -211,6 +208,9 @@ unsigned allocate_vector_exp(ivl_expr_t exp, unsigned wid)
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/*
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* $Log: vector.c,v $
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* Revision 1.5 2005/01/24 05:08:02 steve
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* Part selects are done in the compiler, not here.
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*
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* Revision 1.4 2003/07/03 17:44:10 steve
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* Wider thread vector limit.
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*
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