Refactor code to reduce indentation level.

In preparation for next commit. No functional change.
This commit is contained in:
Martin Whitaker 2024-02-02 22:24:18 +00:00
parent 4667927377
commit 73897b2af6
2 changed files with 27 additions and 15 deletions

View File

@ -423,6 +423,8 @@ class PEIdent : public PExpr {
private:
NetAssign_ *elaborate_lval_array_(Design *des, NetScope *scope,
bool is_force, NetNet *reg) const;
NetAssign_ *elaborate_lval_var_(Design *des, NetScope *scope,
bool is_force, bool is_cassign,
NetNet *reg, ivl_type_t data_type,

View File

@ -250,21 +250,7 @@ NetAssign_*PEIdent::elaborate_lval_var_(Design *des, NetScope *scope,
// slice. Detect the situation by noting if the index count
// is less than the array dimensions (unpacked).
if (reg->unpacked_dimensions() > name_tail.index.size()) {
if (gn_system_verilog()) {
if (name_tail.index.empty()) {
NetAssign_*lv = new NetAssign_(reg);
return lv;
}
cerr << get_fileline() << ": sorry: Assignment to an "
" array slice is not yet supported."
<< endl;
} else {
cerr << get_fileline() << ": error: Assignment to an entire"
" array or to an array slice requires SystemVerilog."
<< endl;
}
des->errors += 1;
return 0;
return elaborate_lval_array_(des, scope, is_force, reg);
}
/* Get the signal referenced by the identifier, and make sure
@ -363,6 +349,30 @@ NetAssign_*PEIdent::elaborate_lval_var_(Design *des, NetScope *scope,
return lv;
}
NetAssign_*PEIdent::elaborate_lval_array_(Design *des, NetScope *,
bool is_force, NetNet *reg) const
{
if (!gn_system_verilog()) {
cerr << get_fileline() << ": error: Assignment to an entire"
" array or to an array slice requires SystemVerilog."
<< endl;
des->errors += 1;
return 0;
}
const name_component_t&name_tail = path_.back();
if (name_tail.index.empty()) {
NetAssign_*lv = new NetAssign_(reg);
return lv;
}
cerr << get_fileline() << ": sorry: Assignment to an "
" array slice is not yet supported."
<< endl;
des->errors += 1;
return 0;
}
NetAssign_* PEIdent::elaborate_lval_net_word_(Design*des,
NetScope*scope,
NetNet*reg,