VHDL named types work in more places.

This commit is contained in:
Stephen Williams 2012-05-05 16:55:29 -07:00
parent 2443884779
commit 369a0b9eca
3 changed files with 26 additions and 11 deletions

View File

@ -350,6 +350,10 @@ int ExpAggregate::elaborate_expr(Entity*ent, Architecture*arc, const VType*ltype
set_type(ltype);
while (const VTypeDef*cur = dynamic_cast<const VTypeDef*>(ltype)) {
ltype = cur->peek_definition();
}
if (const VTypeArray*larray = dynamic_cast<const VTypeArray*>(ltype)) {
return elaborate_expr_array_(ent, arc, larray);
}

View File

@ -238,6 +238,10 @@ class VTypeDef : public VType {
// then this must be used to set the definition later.
void set_definition(const VType*is);
// In some situations, we only need the definition of the
// type, and this method gets it for us.
inline const VType* peek_definition(void) const { return type_; }
void write_to_stream(std::ostream&fd) const;
void write_type_to_stream(ostream&fd) const;
int emit_typedef(std::ostream&out) const;

View File

@ -57,13 +57,19 @@ int VTypeArray::emit_def(ostream&out) const
cur = sub;
}
const VTypePrimitive*base = dynamic_cast<const VTypePrimitive*> (cur->etype_);
assert(base != 0);
assert(dimensions() == 1);
const VType*raw_base = cur->etype_;
base->emit_primitive_type(out);
if (signed_flag_)
out << " signed";
const VTypePrimitive*base = dynamic_cast<const VTypePrimitive*> (raw_base);
if (base) {
assert(dimensions() == 1);
base->emit_def(out);
if (signed_flag_)
out << " signed";
} else {
raw_base->emit_def(out);
}
dims.push_back(cur);
@ -125,8 +131,8 @@ int VTypePrimitive::emit_def(ostream&out) const
int VTypeRange::emit_def(ostream&out) const
{
int errors = 0;
assert(0);
out << "/* Internal error: Don't know how to emit type */";
out << "/* Internal error: Don't know how to emit range */";
errors += base_->emit_def(out);
return errors;
}
@ -147,10 +153,10 @@ int VTypeRecord::emit_def(ostream&out) const
return errors;
}
int VTypeDef::emit_def(ostream&) const
int VTypeDef::emit_def(ostream&out) const
{
int errors = 0;
assert(0);
errors += type_->emit_def(out);
return errors;
}
@ -162,7 +168,8 @@ int VTypeDef::emit_decl(ostream&out, perm_string name, bool reg_flag) const
else
out << "wire ";
out << "\\" << name_ << " \\" << name << " ";
errors += type_->emit_def(out);
out << " \\" << name << " ";
return errors;
}