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Add missing gold and fix VHDL inout test

This commit is contained in:
Cary R 2025-07-01 00:00:53 -07:00
parent 66d57628bf
commit f82c6c7b3a
2 changed files with 10 additions and 2 deletions
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7
ivtest/gold/br_gh1222.gold Normal file
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./ivltests/br_gh1222.v:6: error: variable rout_ca1; cannot be driven by a primitive or continuous assignment with non-default strength.
./ivltests/br_gh1222.v:6: error: variable rout_ca2; cannot be driven by a primitive or continuous assignment with non-default strength.
./ivltests/br_gh1222.v:7: error: variable lout_ca1; cannot be driven by a primitive or continuous assignment with non-default strength.
./ivltests/br_gh1222.v:7: error: variable lout_ca2; cannot be driven by a primitive or continuous assignment with non-default strength.
./ivltests/br_gh1222.v:12: error: variable rout_gt; cannot be driven by a primitive or continuous assignment with non-default strength.
./ivltests/br_gh1222.v:13: error: variable lout_gt; cannot be driven by a primitive or continuous assignment with non-default strength.
10 error(s) during elaboration.

5
ivtest/ivltests/vhdl_inout.v
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@ -1,4 +1,4 @@
// Copyright (c) 2015 CERN
// Copyright (c) 2015-2025 CERN
// @author Maciej Suminski <maciej.suminski@cern.ch>
//
// This source code is free software; you can redistribute it
@ -20,7 +20,8 @@
// Test for port inout mode.
module vhdl_inout_test;
logic a, b, c;
wire a; // An inout port cannot connect to a variable, so make it a wire.
logic b, c;
vhdl_inout dut(a, b, c);
initial begin