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Spelling patches from Larry.

This commit is contained in:
steve 2005-09-19 21:45:35 +00:00
parent e2a1b90b12
commit be73be8c98
13 changed files with 65 additions and 44 deletions
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2
README.txt
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@ -114,7 +114,7 @@ configure script that modify its behavior:
If you are building for Linux/AMD64 (a.k.a x86_64) then to get the
most out of your install, first make sure you have both 64bit and
32bit development libraries installed. Then configure with this
somewhat more compilcated command:
somewhat more complicated command:
./configure libdir64='$(prefix)/lib64' vpidir1=vpi64 vpidir2=. --enable-vvp32

7
elab_expr.cc
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@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: elab_expr.cc,v 1.96 2005/09/14 02:53:13 steve Exp $"
#ident "$Id: elab_expr.cc,v 1.97 2005/09/19 21:45:35 steve Exp $"
#endif
# include "config.h"
@ -765,7 +765,7 @@ NetExpr* PEIdent::elaborate_expr(Design*des, NetScope*scope,
// Non-constant bit select? punt and make a subsignal
// device to mux the bit in the net. This is a fairly
// compilcated task because we need to generate
// complicated task because we need to generate
// expressions to convert calculated bit select
// values to canonical values that are used internally.
if (msb_) {
@ -1048,6 +1048,9 @@ NetExpr* PEUnary::elaborate_expr(Design*des, NetScope*scope, bool) const
/*
* $Log: elab_expr.cc,v $
* Revision 1.97 2005/09/19 21:45:35 steve
* Spelling patches from Larry.
*
* Revision 1.96 2005/09/14 02:53:13 steve
* Support bool expressions and compares handle them optimally.
*

4
extensions.txt
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@ -21,9 +21,9 @@ apparently been absorbed by the IEEE1800 SystemVerilog
standard. Icarus Verilog currently only takes the new primitive types
from the proposal.
Extended data types seperates the concept of net/variable from the
Extended data types separates the concept of net/variable from the
data type. Both nets and variables can declared with any data
type. The primitive types avaialable are:
type. The primitive types available are:
logic - The familiar 0, 1, x and z, optionally with strength.
bool - Limited to only 0 and 1

11
ivl_target.h
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@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: ivl_target.h,v 1.160 2005/09/01 04:11:37 steve Exp $"
#ident "$Id: ivl_target.h,v 1.161 2005/09/19 21:45:35 steve Exp $"
#endif
#ifdef __cplusplus
@ -613,7 +613,7 @@ extern unsigned ivl_expr_width(ivl_expr_t net);
* address to get to a canonical (0-based) address. This value is
* used when external code wishes to access a word. All the
* compiled references to the word within the compiled design are
* converted to cannonical form by the compiler.
* converted to canonical form by the compiler.
*
* ivl_memory_size
* ivl_memory_width
@ -941,7 +941,7 @@ extern const char* ivl_udp_name(ivl_udp_t net);
* Read or write, the ivl_lpm_select nexus is the address. The
* ivl_lpm_selects function returns the vector width of the
* address. The range of the address is always from 0 to the memory
* size-1 -- the cannonical form. It is up to the compiler to generate
* size-1 -- the canonical form. It is up to the compiler to generate
* offsets to correct for a range declaration.
*
* Read ports use the ivl_lpm_q as the data output, and write ports
@ -1084,7 +1084,7 @@ extern ivl_memory_t ivl_lpm_memory(ivl_lpm_t net);
* signal (or even 1) if only a part of the l-value signal is to be
* assigned.
*
* The ivl_lval_part_off is the cannonical base of a constant part or
* The ivl_lval_part_off is the canonical base of a constant part or
* bit select. If the bit select base is non-constant, then the
* ivl_lval_mux will contain an expression. If there is a mux
* expression, then the ivl_lval_part_off result can be ignored.
@ -1671,6 +1671,9 @@ _END_DECL
/*
* $Log: ivl_target.h,v $
* Revision 1.161 2005/09/19 21:45:35 steve
* Spelling patches from Larry.
*
* Revision 1.160 2005/09/01 04:11:37 steve
* Generate code to handle real valued muxes.
*

2
ivlpp/ivlpp.txt
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@ -37,7 +37,7 @@ valid options include:
Predefine the symbol ``name'' to have the specified
value. If the value is not specified, then ``1'' is
used. This is mostly of use for controlling conditional
compilaiton.
compilation.
This option does *not* override existing `define
directives in the source file.

9
netlist.h
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@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: netlist.h,v 1.350 2005/09/14 02:53:14 steve Exp $"
#ident "$Id: netlist.h,v 1.351 2005/09/19 21:45:36 steve Exp $"
#endif
/*
@ -2826,9 +2826,9 @@ class NetEParam : public NetExpr {
* selected from it. The base is the expression that identifies the
* lsb of the expression, and the wid is the width of the part select,
* or 1 for a bit select. No matter what the subexpression is, the
* base is translated in cannonical bits. It is up to the elaborator
* base is translated in canonical bits. It is up to the elaborator
* to figure this out and adjust the expression if the subexpression
* has a non-cannonical base or direction.
* has a non-canonical base or direction.
*
* If the base expression is null, then this expression node can be
* used to express width expansion, signed or unsigned depending on
@ -3444,6 +3444,9 @@ extern ostream& operator << (ostream&, NetNet::Type);
/*
* $Log: netlist.h,v $
* Revision 1.351 2005/09/19 21:45:36 steve
* Spelling patches from Larry.
*
* Revision 1.350 2005/09/14 02:53:14 steve
* Support bool expressions and compares handle them optimally.
*

7
tgt-fpga/fpga.txt
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@ -2,7 +2,7 @@
FPGA LOADABLE CODE GENERATOR FOR Icarus Verilog
Copyright 2001 Stephen Williams
$Id: fpga.txt,v 1.11 2003/08/07 05:17:34 steve Exp $
$Id: fpga.txt,v 1.12 2005/09/19 21:45:36 steve Exp $
The FPGA code generator supports a variety of FPGA devices, writing
XNF or EDIF depending on the target. You can select the architecture
@ -44,7 +44,7 @@ map to target gates if desired.
If this is selected, then the output is formatted as an XNF file,
suitable for most any type of device. The devices that it emits
are generic devices from the unified library. Some devices are macros,
youmay need to further resolve the generated XNF to get working
you may need to further resolve the generated XNF to get working
code for your part.
* arch=virtex
@ -188,6 +188,9 @@ Compile a single-file design with command line tools like so:
---
$Log: fpga.txt,v $
Revision 1.12 2005/09/19 21:45:36 steve
Spelling patches from Larry.
Revision 1.11 2003/08/07 05:17:34 steve
Add arch=lpm to the documentation.

7
tgt-vvp/eval_expr.c
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@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: eval_expr.c,v 1.124 2005/09/19 20:18:20 steve Exp $"
#ident "$Id: eval_expr.c,v 1.125 2005/09/19 21:45:36 steve Exp $"
#endif
# include "vvp_priv.h"
@ -1550,7 +1550,7 @@ static struct vector_info draw_signal_expr(ivl_expr_t exp, unsigned wid,
/*
* Draw code to evaluate a memory word index expression and write the
* value into index register 3. This expression converts the run-time
* calculated value to cannonical form that the %load/mv takes.
* calculated value to canonical form that the %load/mv takes.
*/
void draw_memory_index_expr(ivl_memory_t mem, ivl_expr_t ae)
{
@ -2168,6 +2168,9 @@ struct vector_info draw_eval_expr(ivl_expr_t exp, int stuff_ok_flag)
/*
* $Log: eval_expr.c,v $
* Revision 1.125 2005/09/19 21:45:36 steve
* Spelling patches from Larry.
*
* Revision 1.124 2005/09/19 20:18:20 steve
* Fix warnings about uninitialized variables.
*

24
vvp/README.txt
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@ -1,7 +1,7 @@
/*
* Copyright (c) 2001 Stephen Williams (steve@icarus.com)
*
* $Id: README.txt,v 1.70 2005/07/13 04:58:29 steve Exp $
* $Id: README.txt,v 1.71 2005/09/19 21:45:36 steve Exp $
*/
VVP SIMULATION ENGINE
@ -55,7 +55,7 @@ compiler scales time values ahead of time.
The value is the size of a simulation tick in seconds, and is
expressed as a power of 10. For example, +0 is 1 second, and -9 is 1
nano-second. If the record is left out, then the precision is taken to
nanosecond. If the record is left out, then the precision is taken to
be +0.
LABELS AND SYMBOLS
@ -308,7 +308,7 @@ functor pointer, though.
MEMORY STATEMENTS:
Memories are arrays of words, each word a vvp_vector4_t vector of the
same width. The memory is cannonically addressed as a 1-dimensional
same width. The memory is canonically addressed as a 1-dimensional
array of words, although indices are stored with the memory for
calculating a canonical address from a multi-dimensional address.
@ -326,22 +326,22 @@ memory array and makes it available to procedural code.
Procedural access to the memory references the memory as single array
of words, with the base address==0, and the last address the size (in
words) of the memory -1. It is up to the compiler to convert Verilog
index sets to a cannonical address. The multi-dimensional index set is
index sets to a canonical address. The multi-dimensional index set is
available for VPI use.
Structural read access is implemented in terms of address and data
ports. The addresses applied to the address port are expected to be
in cannonical form.
in canonical form.
A read port is a functor that takes a single input, the read address,
and outputs the word value at the given (cannonical) address.
and outputs the word value at the given (canonical) address.
<label> .mem/port <memid>, <address> ;
<label> identifies the vector of output functors, to allow connections
to the data output. <memid> is the label of the memory.
Any address inputchange, or any change in the addressed memory
Any address input change, or any change in the addressed memory
contents, is immediately propagated to the port output.
A write port is a superset of a read port. It is a 4-input functor
@ -364,8 +364,8 @@ To initialize a memory, use:
.mem/init <memid> <start>, val , val ... ;
<memid> is the label of the memory, and the <start> is the start
address (cannonical) of the first word to be initialized. The start
address allows mustliple statements be used to initialize words of a
address (canonical) of the first word to be initialized. The start
address allows multiple statements be used to initialize words of a
memory.
The values are one per word.
@ -441,7 +441,7 @@ PART SELECT STATEMENTS:
Part select statements are functors with three inputs. They take in at
port-0 a vector, and output a selected (likely smaller) part of that
vector. The other inputs specify what those parts are, as a cannonical
vector. The other inputs specify what those parts are, as a canonical
bit number, and a width. Normally, those bits are constant values.
<label> .part <symbol>, <base>, <wid>;
@ -464,7 +464,7 @@ base of the part select. Thus, the part select can move around.
PART CONCATENATION STATEMENTS:
The opposite of the part select statement is the part concatenation
statement. The .concat statment is a functor node that takes at input
statement. The .concat statement is a functor node that takes at input
vector values and produces a single vector output that is the
concatenation of all the inputs.
@ -572,7 +572,7 @@ are the same concept, but for the continuous assign port.
STRUCTURAL ARITHMETIC STATEMENTS:
The various Verilog arithmetic operators (+-*/%) ar avaiable to
The various Verilog arithmetic operators (+-*/%) are available to
structural contexts as two-input functors that take in vectors. All of
these operators take two inputs and generate a fixed width output. The
input vectors will be padded if needed to get the desired output width.

18
vvp/opcodes.txt
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@ -1,7 +1,7 @@
/*
* Copyright (c) 2001-2003 Stephen Williams (steve@icarus.com)
*
* $Id: opcodes.txt,v 1.67 2005/09/17 04:01:02 steve Exp $
* $Id: opcodes.txt,v 1.68 2005/09/19 21:45:37 steve Exp $
*/
@ -71,10 +71,10 @@ labeled memory. The <delay> is the delay in simulation time to the
assignment (0 for non-blocking assignment) and the <bit> is the base
of the vector to write.
The width of the word is retrived from index register 0.
The width of the word is retrieved from index register 0.
The address of the word in the memory is from index register 3. The
address is cannonical form.
address is canonical form.
* %assign/v0 <var-label>, <delay>, <bit>
* %assign/v0/d <var-label>, <delayx>, <bit>
@ -206,7 +206,7 @@ Only bit 4 is set by these instructions.
* %cvt/vr <bit-l>, <bit-r>, <wid>
Copy a word from r to l, converting it from real to integer (ir) or
integer to real (ri) in the process. The source and destinaition may
integer to real (ri) in the process. The source and destination may
be the same word address, leading to a convert in place.
The %cvt/vr opcode converts a real word <bit-r> to a thread vector
@ -365,7 +365,7 @@ instruction loads only a single bit.
* %load/mv <bit>, <memory-label>, <wid>
this inctruction loads a word from the specified memory. The word
this instruction loads a word from the specified memory. The word
address is in index register 3. The width should match the width of
the memory word.
@ -393,7 +393,7 @@ register.
* %load/x.p <bit>, <functor-label>, <idx>
This is an indexed load. It uses the contents of the specified index
register to select a bit from a vectur functor at <functor-label>. The
register to select a bit from a vector functor at <functor-label>. The
bit is pulled from the indexed bit of the addressed functor and loaded
into the destination thread bit. If the indexed value is beyond the
width of the vector, then the result is X.
@ -521,7 +521,7 @@ forced value until another value propagates through.
This sets a vector to a variable, and is used to implement blocking
assignments. The <var-label> identifies the variable to receive the
new value. Once the set completes, the vlaue is immediately available
new value. Once the set completes, the value is immediately available
to be read out of the variable. The <bit> is the address of the thread
register that contains the LSB of the vector, and the <wid> is the
size of the vector. The width must exactly match the width of the
@ -545,9 +545,9 @@ This instruction writes a real word to the specified VPI-like object.
This sets the part of a signal vector, the address calculated by
using the index register 0 to index the base within the vector of
<var-label>. The destination must be a signal of some sort. Otherwise,
the instrution will fail.
the instruction will fail.
The addressing is cannonical (0-based) so the compiler must figure out
The addressing is canonical (0-based) so the compiler must figure out
non-zero offsets, if any. The width is the width of the part being
written. The other bits of the vector are not touched.

7
vvp/vthread.cc
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@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: vthread.cc,v 1.147 2005/09/17 04:01:02 steve Exp $"
#ident "$Id: vthread.cc,v 1.148 2005/09/19 21:45:37 steve Exp $"
#endif
# include "config.h"
@ -619,7 +619,7 @@ bool of_ASSIGN_MEM(vthread_t thr, vvp_code_t cp)
/* %assign/mv <memory>, <delay>, <bit>
* This generates an assignment event to a memory. Index register 0
* contains the width of the vector (and the word) and index register
* 3 contains the cannonical address of the word in memory.
* 3 contains the canonical address of the word in memory.
*/
bool of_ASSIGN_MV(vthread_t thr, vvp_code_t cp)
{
@ -3187,6 +3187,9 @@ bool of_JOIN_UFUNC(vthread_t thr, vvp_code_t cp)
/*
* $Log: vthread.cc,v $
* Revision 1.148 2005/09/19 21:45:37 steve
* Spelling patches from Larry.
*
* Revision 1.147 2005/09/17 04:01:02 steve
* Add the load/v.p instruction.
*

4
vvp/vthread.txt
View File

@ -1,7 +1,7 @@
/*
* Copyright (c) 2001 Stephen Williams (steve@icarus.com)
*
* $Id: vthread.txt,v 1.5 2005/09/14 02:50:07 steve Exp $
* $Id: vthread.txt,v 1.6 2005/09/19 21:45:37 steve Exp $
*/
@ -40,7 +40,7 @@ The remaining 64K-8 possible <bit> values are read-write bit registers
that can be accessed singly or as vectors. This obviously implies that
a bit address is 16 bits.
Threads alco contait 16 numeric registers. These registers can hold a
Threads also contain 16 numeric registers. These registers can hold a
real value or a 64bit integer, and can be used in certain cases where
numeric values are needed. The thread instruction set includes
%ix/* instructions to manipulate these registers. The instructions

7
vvp/vvp_net.h
View File

@ -18,7 +18,7 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ident "$Id: vvp_net.h,v 1.44 2005/08/27 02:34:43 steve Exp $"
#ident "$Id: vvp_net.h,v 1.45 2005/09/19 21:45:37 steve Exp $"
# include "config.h"
# include <stddef.h>
@ -975,7 +975,7 @@ extern void vvp_send_long(vvp_net_ptr_t ptr, long val);
* exactly match the <wid> vector.
*
* The <base> is where in the receiver the bit vector is to be
* written. This address is given in cannonical units; 0 is the LSB, 1
* written. This address is given in canonical units; 0 is the LSB, 1
* is the next bit, and so on.
*
* The <vwid> is the width of the destination vector that this part is
@ -999,6 +999,9 @@ inline void vvp_send_vec4_pv(vvp_net_ptr_t ptr, const vvp_vector4_t&val,
/*
* $Log: vvp_net.h,v $
* Revision 1.45 2005/09/19 21:45:37 steve
* Spelling patches from Larry.
*
* Revision 1.44 2005/08/27 02:34:43 steve
* Bring threads into the vvp_vector4_t structure.
*