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Fix typo in verilog.spec it should be blif.tgt not blif.txt

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Cary R 2013-08-06 17:15:58 -07:00
parent 7c0a75cf0c
commit 71552b7d1a
1 changed files with 1 additions and 1 deletions
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verilog.spec
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@ -68,7 +68,7 @@ rm -rf $RPM_BUILD_ROOT
%attr(-,root,root) %{_libdir}/ivl%{suff}/ivl
%attr(-,root,root) %{_libdir}/ivl%{suff}/ivlpp
%attr(-,root,root) %{_libdir}/ivl%{suff}/vhdlpp
%attr(-,root,root) %{_libdir}/ivl%{suff}/blif.txt
%attr(-,root,root) %{_libdir}/ivl%{suff}/blif.tgt
%attr(-,root,root) %{_libdir}/ivl%{suff}/blif.conf
%attr(-,root,root) %{_libdir}/ivl%{suff}/blif-s.conf
%attr(-,root,root) %{_libdir}/ivl%{suff}/null.tgt