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Synthesis of assignment that is part of larger block. 

It is possible for an assignment statement to be part of a
grander complex that has lots of outputs, not all handled
by this particular assignment. In that case, the assignment
may need to figure out which output it is supposed to bind to.
This commit is contained in:
Stephen Williams 2014-05-03 15:45:15 -07:00
parent ce864fc634
commit 109c5d895d
1 changed files with 14 additions and 3 deletions
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17
synth2.cc
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@ -136,10 +136,21 @@ bool NetAssignBase::synth_async(Design*des, NetScope*scope,
rsig = tmp;
}
ivl_assert(*this, nex_out.pin_count()==1);
ivl_assert(*this, rsig->pin_count()==1);
connect(nex_out.pin(0), rsig->pin(0));
if (nex_out.pin_count() > 1) {
NexusSet tmp_set;
nex_output(tmp_set);
ivl_assert(*this, tmp_set.size()==1);
unsigned ptr = nex_map.find_nexus(tmp_set[0]);
ivl_assert(*this, rsig->pin_count()==1);
ivl_assert(*this, nex_map.size()==nex_out.pin_count());
ivl_assert(*this, nex_out.pin_count() > ptr);
connect(nex_out.pin(ptr), rsig->pin(0));
} else {
ivl_assert(*this, nex_out.pin_count()==1);
ivl_assert(*this, rsig->pin_count()==1);
connect(nex_out.pin(0), rsig->pin(0));
}
/* This lval_ represents a reg that is a WIRE in the
synthesized results. This function signals the destructor