Add check target to tgt-verilog/Makefile.in

Add the missing check target to Makefile.in.
2008-01-16 10:51:32 -08:00 · 2008-01-16 10:51:32 -08:00 · 0fa223434e
parent e1bf2ec019
commit 0fa223434e
1 changed files with 2 additions and 0 deletions
--- a/tgt-verilog/Makefile.in
+++ b/tgt-verilog/Makefile.in
@ -70,6 +70,8 @@ clean:
 distclean: clean
 	rm -f Makefile

+check: all
+
 install: all installdirs $(libdir)/ivl/verilog.tgt \
 	$(includedir)/vpi_user.h