reg can take unsigned as well as signed.
SystemVerilog adds "unsigned" so that it can be explicit as well as implicit.
This commit is contained in:
Stephen Williams
parent
b081818a90
commit
9037354c6b
79
parse.y
79
parse.y
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@ -330,7 +330,7 @@ static PECallFunction*make_call_function(perm_string tn, PExpr*arg1, PExpr*arg2)
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%type <flag> from_exclude
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%type <number> number
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%type <flag> signed_opt signed_unsigned_opt
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%type <flag> unsigned_signed_opt signed_unsigned_opt
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%type <flag> udp_reg_opt edge_operator automatic_opt
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%type <drive> drive_strength drive_strength_opt dr_strength0 dr_strength1
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%type <letter> udp_input_sym udp_output_sym
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@ -508,7 +508,7 @@ attribute
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block_item_decl
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: attribute_list_opt K_reg
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primitive_type_opt signed_opt range
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primitive_type_opt unsigned_signed_opt range
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register_variable_list ';'
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{ ivl_variable_type_t dtype = $3;
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if (dtype == IVL_VT_NO_TYPE)
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@ -521,7 +521,7 @@ block_item_decl
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range. This is the rule for a scalar. */
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| attribute_list_opt K_reg
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primitive_type_opt signed_opt
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primitive_type_opt unsigned_signed_opt
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register_variable_list ';'
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{ ivl_variable_type_t dtype = $3;
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if (dtype == IVL_VT_NO_TYPE)
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@ -1900,7 +1900,7 @@ list_of_port_declarations
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port_declaration
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: attribute_list_opt
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K_input net_type_opt primitive_type_opt signed_opt range_opt IDENTIFIER
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K_input net_type_opt primitive_type_opt unsigned_signed_opt range_opt IDENTIFIER
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{ Module::port_t*ptmp;
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perm_string name = lex_strings.make($7);
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ptmp = pform_module_port_reference(name, @2.text,
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@ -1937,7 +1937,7 @@ port_declaration
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$$ = ptmp;
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}
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| attribute_list_opt
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K_inout net_type_opt primitive_type_opt signed_opt range_opt IDENTIFIER
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K_inout net_type_opt primitive_type_opt unsigned_signed_opt range_opt IDENTIFIER
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{ Module::port_t*ptmp;
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perm_string name = lex_strings.make($7);
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ptmp = pform_module_port_reference(name, @2.text,
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@ -1955,7 +1955,7 @@ port_declaration
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$$ = ptmp;
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}
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| attribute_list_opt
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K_output net_type_opt primitive_type_opt signed_opt range_opt IDENTIFIER
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K_output net_type_opt primitive_type_opt unsigned_signed_opt range_opt IDENTIFIER
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{ Module::port_t*ptmp;
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perm_string name = lex_strings.make($7);
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ptmp = pform_module_port_reference(name, @2.text,
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@ -1973,7 +1973,7 @@ port_declaration
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$$ = ptmp;
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}
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| attribute_list_opt
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K_output var_type primitive_type_opt signed_opt range_opt IDENTIFIER
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K_output var_type primitive_type_opt unsigned_signed_opt range_opt IDENTIFIER
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{ Module::port_t*ptmp;
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perm_string name = lex_strings.make($7);
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ptmp = pform_module_port_reference(name, @2.text,
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@ -1991,7 +1991,7 @@ port_declaration
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$$ = ptmp;
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}
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| attribute_list_opt
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K_output var_type primitive_type_opt signed_opt range_opt IDENTIFIER '=' expression
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K_output var_type primitive_type_opt unsigned_signed_opt range_opt IDENTIFIER '=' expression
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{ Module::port_t*ptmp;
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perm_string name = lex_strings.make($7);
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ptmp = pform_module_port_reference(name, @2.text,
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@ -2049,9 +2049,10 @@ net_type_opt
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* "true". This corresponds to the declaration defaults for
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* byte/shortint/int/longint.
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*/
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signed_opt
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: K_signed { $$ = true; }
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| {$$ = false; }
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unsigned_signed_opt
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: K_signed { $$ = true; }
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| K_unsigned { $$ = false; }
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| { $$ = false; }
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;
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signed_unsigned_opt
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@ -2206,7 +2207,7 @@ module_item
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resort to the default type LOGIC. */
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: attribute_list_opt net_type
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primitive_type_opt signed_opt range_opt
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primitive_type_opt unsigned_signed_opt range_opt
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delay3_opt
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net_variable_list ';'
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@ -2227,7 +2228,7 @@ module_item
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declarations. */
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| attribute_list_opt net_type
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primitive_type_opt signed_opt range_opt
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primitive_type_opt unsigned_signed_opt range_opt
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delay3_opt net_decl_assigns ';'
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{ ivl_variable_type_t dtype = $3;
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@ -2246,7 +2247,7 @@ module_item
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gives strength to the assignment drivers. */
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| attribute_list_opt net_type
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primitive_type_opt signed_opt
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primitive_type_opt unsigned_signed_opt
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drive_strength net_decl_assigns ';'
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{ ivl_variable_type_t dtype = $3;
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@ -2266,7 +2267,7 @@ module_item
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delete $4;
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}
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| port_type signed_opt range_opt delay3_opt list_of_identifiers ';'
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| port_type unsigned_signed_opt range_opt delay3_opt list_of_identifiers ';'
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{ pform_set_port_type(@1, $5, $3, $2, $1);
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}
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@ -2274,12 +2275,12 @@ module_item
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input wire signed [h:l] <list>;
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This creates the wire and sets the port type all at once. */
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| port_type net_type signed_opt range_opt list_of_identifiers ';'
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| port_type net_type unsigned_signed_opt range_opt list_of_identifiers ';'
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{ pform_makewire(@1, $4, $3, $5, $2, $1, IVL_VT_NO_TYPE, 0,
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SR_BOTH);
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}
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| K_output var_type signed_opt range_opt list_of_port_identifiers ';'
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| K_output var_type unsigned_signed_opt range_opt list_of_port_identifiers ';'
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{ list<pair<perm_string,PExpr*> >::const_iterator pp;
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list<perm_string>*tmp = new list<perm_string>;
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for (pp = $5->begin(); pp != $5->end(); pp++) {
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@ -2299,19 +2300,19 @@ module_item
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because the port declaration implies an external driver, which
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cannot be attached to a reg. These rules catch that error early. */
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| K_input var_type signed_opt range_opt list_of_identifiers ';'
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| K_input var_type unsigned_signed_opt range_opt list_of_identifiers ';'
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{ pform_makewire(@1, $4, $3, $5, $2, NetNet::PINPUT,
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IVL_VT_NO_TYPE, 0);
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yyerror(@2, "error: reg variables cannot be inputs.");
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}
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| K_inout var_type signed_opt range_opt list_of_identifiers ';'
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| K_inout var_type unsigned_signed_opt range_opt list_of_identifiers ';'
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{ pform_makewire(@1, $4, $3, $5, $2, NetNet::PINOUT,
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IVL_VT_NO_TYPE, 0);
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yyerror(@2, "error: reg variables cannot be inouts.");
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}
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| port_type signed_opt range_opt delay3_opt error ';'
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| port_type unsigned_signed_opt range_opt delay3_opt error ';'
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{ yyerror(@1, "error: Invalid variable list"
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" in port declaration.");
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if ($3) delete $3;
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@ -3284,8 +3285,9 @@ dimensions
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/* This is used to express the return type of a function. */
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function_range_or_type_opt
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: range { $$.range = $1; $$.type = PTF_REG; }
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| K_signed range { $$.range = $2; $$.type = PTF_REG_S; }
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: range { $$.range = $1; $$.type = PTF_REG; }
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| K_signed range { $$.range = $2; $$.type = PTF_REG_S; }
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| K_unsigned range { $$.range = $2; $$.type = PTF_REG; }
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| K_integer { $$.range = 0; $$.type = PTF_INTEGER; }
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| K_real { $$.range = 0; $$.type = PTF_REAL; }
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| K_realtime { $$.range = 0; $$.type = PTF_REALTIME; }
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@ -4131,30 +4133,27 @@ reg_opt
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task_port_item
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: K_input reg_opt signed_opt range_opt list_of_identifiers ';'
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{ svector<PWire*>*tmp
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= pform_make_task_ports(NetNet::PINPUT,
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: K_input reg_opt unsigned_signed_opt range_opt list_of_identifiers ';'
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{ svector<PWire*>*tmp = pform_make_task_ports(NetNet::PINPUT,
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IVL_VT_NO_TYPE, $3,
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$4, $5,
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@1.text, @1.first_line);
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$$ = tmp;
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}
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| K_output reg_opt signed_opt range_opt list_of_identifiers ';'
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{ svector<PWire*>*tmp
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= pform_make_task_ports(NetNet::POUTPUT,
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$$ = tmp;
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}
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| K_output reg_opt unsigned_signed_opt range_opt list_of_identifiers ';'
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{ svector<PWire*>*tmp = pform_make_task_ports(NetNet::POUTPUT,
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IVL_VT_LOGIC, $3,
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$4, $5,
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@1.text, @1.first_line);
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$$ = tmp;
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}
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| K_inout reg_opt signed_opt range_opt list_of_identifiers ';'
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{ svector<PWire*>*tmp
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= pform_make_task_ports(NetNet::PINOUT,
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$$ = tmp;
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}
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| K_inout reg_opt unsigned_signed_opt range_opt list_of_identifiers ';'
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{ svector<PWire*>*tmp = pform_make_task_ports(NetNet::PINOUT,
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IVL_VT_LOGIC, $3,
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$4, $5,
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@1.text, @1.first_line);
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$$ = tmp;
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}
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$$ = tmp;
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}
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/* When the port is an integer, infer a signed vector of the integer
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shape. Generate a range ([31:0]) to make it work. */
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@ -4298,7 +4297,7 @@ task_item_list_opt
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task_port_decl
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: K_input reg_opt signed_opt range_opt IDENTIFIER
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: K_input reg_opt unsigned_signed_opt range_opt IDENTIFIER
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{ port_declaration_context.port_type = NetNet::PINPUT;
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port_declaration_context.var_type = IVL_VT_LOGIC;
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port_declaration_context.sign_flag = $3;
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@ -4312,7 +4311,7 @@ task_port_decl
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$$ = tmp;
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}
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| K_output reg_opt signed_opt range_opt IDENTIFIER
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| K_output reg_opt unsigned_signed_opt range_opt IDENTIFIER
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{ port_declaration_context.port_type = NetNet::POUTPUT;
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port_declaration_context.var_type = IVL_VT_LOGIC;
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port_declaration_context.sign_flag = $3;
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@ -4325,7 +4324,7 @@ task_port_decl
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@1.text, @1.first_line);
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$$ = tmp;
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}
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| K_inout reg_opt signed_opt range_opt IDENTIFIER
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| K_inout reg_opt unsigned_signed_opt range_opt IDENTIFIER
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{ port_declaration_context.port_type = NetNet::PINOUT;
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port_declaration_context.var_type = IVL_VT_LOGIC;
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port_declaration_context.sign_flag = $3;
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