luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Add check that entire array isn't both procedurally and continuously assigned. 

This fixes issue #1090.
This commit is contained in:
Martin Whitaker 2024-02-02 22:49:49 +00:00
parent 73897b2af6
commit a133ae5d9a
1 changed files with 11 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
elab_lval.cc
View File

@ -362,6 +362,17 @@ NetAssign_*PEIdent::elaborate_lval_array_(Design *des, NetScope *,
const name_component_t&name_tail = path_.back();
if (name_tail.index.empty()) {
if ((reg->type()==NetNet::UNRESOLVED_WIRE) && !is_force) {
cerr << get_fileline() << ": error: Cannot perform "
"procedural assign to array '" << reg->name();
if (reg->coerced_to_uwire())
cerr << "' because it is continuously assigned.";
else
cerr << "' because it is an unresolved wire.";
cerr << endl;
des->errors += 1;
return 0;
}
NetAssign_*lv = new NetAssign_(reg);
return lv;
}