DeflateAwning 2023-10-15 19:29:40 -06:00
parent 950d72c77d
commit 95217830b4
5 changed files with 5 additions and 5 deletions

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@ -38,7 +38,7 @@ Icarus Verilog is intended to compile ALL of the Verilog HDL, as
described in the IEEE-1364 standard. Of course, it's not quite there
yet. It does currently handle a mix of structural and behavioural
constructs. For a view of the current state of Icarus Verilog, see its
home page at http://iverilog.icarus.com/.
home page at https://steveicarus.github.io/iverilog/.
Icarus Verilog is not aimed at being a simulator in the traditional
sense, but a compiler that generates code employed by back-end

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@ -642,7 +642,7 @@ Steve Williams (steve@icarus.com)
.SH SEE ALSO
vvp(1),
.BR "<http://iverilog.icarus.com/>"
.BR "<https://steveicarus.github.io/iverilog/>"
Tips on using, debugging, and developing the compiler can be found at
.BR "<http://iverilog.wikia.com/>"

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@ -115,7 +115,7 @@ Steve Williams (steve@icarus.com)
.SH SEE ALSO
iverilog(1), vvp(1),
.BR "<http://iverilog.icarus.com/>",
.BR "<https://steveicarus.github.io/iverilog/>",
.BR "<http://mingw-w64.yaxm.org/>",
.SH COPYRIGHT

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@ -5,7 +5,7 @@ pkgver=ci
pkgrel=1
pkgdesc="Icarus Verilog, a Verilog simulation and synthesis tool (mingw-w64)"
arch=('any')
url="http://iverilog.icarus.com/"
url="https://steveicarus.github.io/iverilog/"
license=('GPLv2+')
depends=("${MINGW_PACKAGE_PREFIX}-readline"
"${MINGW_PACKAGE_PREFIX}-gcc-libs")

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@ -192,7 +192,7 @@ Steve Williams (steve@icarus.com)
.SH SEE ALSO
iverilog(1),
iverilog\-vpi(1),
.BR "<http://iverilog.icarus.com/>"
.BR "<https://steveicarus.github.io/iverilog/>"
.SH COPYRIGHT
.nf