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@ -38,7 +38,7 @@ Icarus Verilog is intended to compile ALL of the Verilog HDL, as
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described in the IEEE-1364 standard. Of course, it's not quite there
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yet. It does currently handle a mix of structural and behavioural
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constructs. For a view of the current state of Icarus Verilog, see its
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home page at http://iverilog.icarus.com/.
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home page at https://steveicarus.github.io/iverilog/.
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Icarus Verilog is not aimed at being a simulator in the traditional
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sense, but a compiler that generates code employed by back-end
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@ -642,7 +642,7 @@ Steve Williams (steve@icarus.com)
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.SH SEE ALSO
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vvp(1),
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.BR "<http://iverilog.icarus.com/>"
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.BR "<https://steveicarus.github.io/iverilog/>"
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Tips on using, debugging, and developing the compiler can be found at
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.BR "<http://iverilog.wikia.com/>"
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@ -115,7 +115,7 @@ Steve Williams (steve@icarus.com)
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.SH SEE ALSO
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iverilog(1), vvp(1),
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.BR "<http://iverilog.icarus.com/>",
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.BR "<https://steveicarus.github.io/iverilog/>",
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.BR "<http://mingw-w64.yaxm.org/>",
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.SH COPYRIGHT
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@ -5,7 +5,7 @@ pkgver=ci
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pkgrel=1
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pkgdesc="Icarus Verilog, a Verilog simulation and synthesis tool (mingw-w64)"
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arch=('any')
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url="http://iverilog.icarus.com/"
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url="https://steveicarus.github.io/iverilog/"
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license=('GPLv2+')
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depends=("${MINGW_PACKAGE_PREFIX}-readline"
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"${MINGW_PACKAGE_PREFIX}-gcc-libs")
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@ -192,7 +192,7 @@ Steve Williams (steve@icarus.com)
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.SH SEE ALSO
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iverilog(1),
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iverilog\-vpi(1),
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.BR "<http://iverilog.icarus.com/>"
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.BR "<https://steveicarus.github.io/iverilog/>"
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.SH COPYRIGHT
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.nf
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