ivtest: Add regression test for undefined intra-assignment delay

Check that assignments with undefined intra-assignment delay get executed
with zero delay. The assignment should not be skipped.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This commit is contained in:
Lars-Peter Clausen 2024-09-02 10:54:45 +02:00
parent 80fd301fc1
commit fa83f42cba
3 changed files with 59 additions and 0 deletions

View File

@ -0,0 +1,54 @@
module test;
// Test that intra-assignment delay values of 'z and 'x get treated as a zero
// delay. Check this for different types of assignments. The assignment should
// not be skipped.
reg failed = 1'b0;
`define check(expr, val) \
if (expr !== val) begin \
$display("FAILED(%0d): `%s`, expected %0x, got %0x", `__LINE__, `"expr`", val, expr); \
failed = 1'b1; \
end
integer delay_x = 32'hx;
wire [31:0] delay_z;
reg [31:0] x;
reg [31:0] a[0:1];
integer i = 0, j = 0;
`define test(var) \
// Non-blocking \
var = 0; \
var <= #delay_x 1; \
#1 `check(var, 1) \
var = 0; \
var <= #delay_z 1; \
#1 `check(var, 1) \
// blocking \
var = 0; \
var = #delay_x 1; \
`check(var, 1) \
var = 0; \
var = #delay_z 1; \
`check(var, 1)
initial begin
`test(x)
`test(x[0])
`test(x[i])
`test(a[0])
`test(a[0][0])
`test(a[0][j])
`test(a[i])
`test(a[i][0])
`test(a[i][j])
if (!failed) begin
$display("PASSED");
end
end
endmodule

View File

@ -266,6 +266,7 @@ vams_abs2 vvp_tests/vams_abs2.json
vams_abs2-vlog95 vvp_tests/vams_abs2-vlog95.json
vams_abs3 vvp_tests/vams_abs3.json
vams_abs3-vlog95 vvp_tests/vams_abs3-vlog95.json
vardly_undefined_vec vvp_tests/vardly_undefined_vec.json
va_math vvp_tests/va_math.json
warn_opt_sys_tf vvp_tests/warn_opt_sys_tf.json
wreal vvp_tests/wreal.json

View File

@ -0,0 +1,4 @@
{
"type" : "normal",
"source" : "vardly_undefined_vec.v"
}