luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Assignment to arrays

This commit is contained in:
Nick Gasson 2008-07-17 13:41:44 +01:00
parent 1d3ac6bc1f
commit 2a791bfb38
2 changed files with 30 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
tgt-vhdl/stmt.cc
View File

@ -117,6 +117,8 @@ static vhdl_expr *make_assign_rhs(ivl_signal_t sig, vhdl_scope *scope,
if (base == NULL)
return rhs->cast(decl->get_type());
else if (decl->get_type()->get_name() == VHDL_TYPE_ARRAY)
return rhs->cast(decl->get_type()->get_base());
else {
// Doesn't make sense to part select on something that's
// not a vector
@ -142,8 +144,12 @@ static vhdl_var_ref *make_assign_lhs(ivl_signal_t sig, vhdl_scope *scope,
vhdl_type *ltype = new vhdl_type(*decl->get_type());
vhdl_var_ref *lval_ref = new vhdl_var_ref(signame.c_str(), ltype);
if (base)
lval_ref->set_slice(base, lval_width - 1);
if (base) {
if (decl->get_type()->get_name() == VHDL_TYPE_ARRAY)
lval_ref->set_slice(base, 0);
else
lval_ref->set_slice(base, lval_width - 1);
}
return lval_ref;
}
@ -167,6 +173,8 @@ static T *make_assignment(vhdl_procedural *proc, stmt_container *container,
vhdl_expr *base = NULL;
ivl_expr_t e_off = ivl_lval_part_off(lval);
if (NULL == e_off)
e_off = ivl_lval_idx(lval);
if (e_off) {
if ((base = translate_expr(e_off)) == NULL)
return NULL;
@ -239,7 +247,9 @@ static T *make_assignment(vhdl_procedural *proc, stmt_container *container,
// internal signals not ports
if (proc->get_scope()->initializing()
&& ivl_signal_port(sig) == IVL_SIP_NONE
&& !decl->has_initial() && rhs->constant()) {
&& !decl->has_initial()
&& rhs->constant()
&& decl->get_type()->get_name() != VHDL_TYPE_ARRAY) {
// If this assignment is not in the top-level container
// it will not be made on all paths through the code

29
tgt-vhdl/vhdl_syntax.cc
View File

@ -507,22 +507,27 @@ vhdl_var_ref::~vhdl_var_ref()
void vhdl_var_ref::set_slice(vhdl_expr *s, int w)
{
assert(type_);
vhdl_type_name_t tname = type_->get_name();
assert(tname == VHDL_TYPE_UNSIGNED || tname == VHDL_TYPE_SIGNED);
slice_ = s;
slice_width_ = w;
vhdl_type_name_t tname = type_->get_name();
if (tname == VHDL_TYPE_ARRAY) {
type_ = new vhdl_type(*type_->get_base());
}
else {
assert(tname == VHDL_TYPE_UNSIGNED || tname == VHDL_TYPE_SIGNED);
if (type_)
delete type_;
if (w > 0)
type_ = new vhdl_type(tname, w);
else
type_ = vhdl_type::std_logic();
if (type_)
delete type_;
if (w > 0)
type_ = new vhdl_type(tname, w);
else
type_ = vhdl_type::std_logic();
}
}
void vhdl_var_ref::emit(std::ostream &of, int level) const
{
of << name_;